Lines Matching defs:rdev
50 static void radeon_debugfs_pm_init(struct radeon_device *rdev);
51 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
52 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
53 static void radeon_pm_update_profile(struct radeon_device *rdev);
54 static void radeon_pm_set_clocks(struct radeon_device *rdev);
56 int radeon_pm_get_type_index(struct radeon_device *rdev,
63 for (i = 0; i < rdev->pm.num_power_states; i++) {
64 if (rdev->pm.power_state[i].type == ps_type) {
71 return rdev->pm.default_power_state_index;
74 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
76 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
77 mutex_lock(&rdev->pm.mutex);
79 rdev->pm.dpm.ac_power = true;
81 rdev->pm.dpm.ac_power = false;
82 if (rdev->family == CHIP_ARUBA) {
83 if (rdev->asic->dpm.enable_bapm)
84 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
86 mutex_unlock(&rdev->pm.mutex);
87 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
88 if (rdev->pm.profile == PM_PROFILE_AUTO) {
89 mutex_lock(&rdev->pm.mutex);
90 radeon_pm_update_profile(rdev);
91 radeon_pm_set_clocks(rdev);
92 mutex_unlock(&rdev->pm.mutex);
97 static void radeon_pm_update_profile(struct radeon_device *rdev)
99 switch (rdev->pm.profile) {
101 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
105 if (rdev->pm.active_crtc_count > 1)
106 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
108 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
110 if (rdev->pm.active_crtc_count > 1)
111 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
113 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
117 if (rdev->pm.active_crtc_count > 1)
118 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
120 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
123 if (rdev->pm.active_crtc_count > 1)
124 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
126 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
129 if (rdev->pm.active_crtc_count > 1)
130 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
132 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
136 if (rdev->pm.active_crtc_count == 0) {
137 rdev->pm.requested_power_state_index =
138 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
139 rdev->pm.requested_clock_mode_index =
140 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
142 rdev->pm.requested_power_state_index =
143 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
144 rdev->pm.requested_clock_mode_index =
145 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
149 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
153 if (list_empty(&rdev->gem.objects))
156 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
162 static void radeon_sync_with_vblank(struct radeon_device *rdev)
164 if (rdev->pm.active_crtcs) {
165 rdev->pm.vblank_sync = false;
167 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
172 static void radeon_set_power_state(struct radeon_device *rdev)
177 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
178 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
181 if (radeon_gui_idle(rdev)) {
182 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
183 clock_info[rdev->pm.requested_clock_mode_index].sclk;
184 if (sclk > rdev->pm.default_sclk)
185 sclk = rdev->pm.default_sclk;
191 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
192 (rdev->family >= CHIP_BARTS) &&
193 rdev->pm.active_crtc_count &&
194 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
195 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
196 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
197 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
199 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
200 clock_info[rdev->pm.requested_clock_mode_index].mclk;
202 if (mclk > rdev->pm.default_mclk)
203 mclk = rdev->pm.default_mclk;
206 if (sclk < rdev->pm.current_sclk)
209 radeon_sync_with_vblank(rdev);
211 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
212 if (!radeon_pm_in_vbl(rdev))
216 radeon_pm_prepare(rdev);
220 radeon_pm_misc(rdev);
223 if (sclk != rdev->pm.current_sclk) {
224 radeon_pm_debug_check_in_vbl(rdev, false);
225 radeon_set_engine_clock(rdev, sclk);
226 radeon_pm_debug_check_in_vbl(rdev, true);
227 rdev->pm.current_sclk = sclk;
232 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
233 radeon_pm_debug_check_in_vbl(rdev, false);
234 radeon_set_memory_clock(rdev, mclk);
235 radeon_pm_debug_check_in_vbl(rdev, true);
236 rdev->pm.current_mclk = mclk;
242 radeon_pm_misc(rdev);
244 radeon_pm_finish(rdev);
246 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
247 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
252 static void radeon_pm_set_clocks(struct radeon_device *rdev)
258 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
259 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
262 down_write(&rdev->pm.mclk_lock);
263 mutex_lock(&rdev->ring_lock);
267 struct radeon_ring *ring = &rdev->ring[i];
271 r = radeon_fence_wait_empty(rdev, i);
274 mutex_unlock(&rdev->ring_lock);
275 up_write(&rdev->pm.mclk_lock);
280 radeon_unmap_vram_bos(rdev);
282 if (rdev->irq.installed) {
284 drm_for_each_crtc(crtc, rdev->ddev) {
285 if (rdev->pm.active_crtcs & (1 << i)) {
288 rdev->pm.req_vblank |= (1 << i);
297 radeon_set_power_state(rdev);
299 if (rdev->irq.installed) {
301 drm_for_each_crtc(crtc, rdev->ddev) {
302 if (rdev->pm.req_vblank & (1 << i)) {
303 rdev->pm.req_vblank &= ~(1 << i);
311 radeon_update_bandwidth_info(rdev);
312 if (rdev->pm.active_crtc_count)
313 radeon_bandwidth_update(rdev);
315 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
317 mutex_unlock(&rdev->ring_lock);
318 up_write(&rdev->pm.mclk_lock);
321 static void radeon_pm_print_states(struct radeon_device *rdev)
327 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
328 for (i = 0; i < rdev->pm.num_power_states; i++) {
329 power_state = &rdev->pm.power_state[i];
332 if (i == rdev->pm.default_power_state_index)
334 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
341 if (rdev->flags & RADEON_IS_IGP)
360 struct radeon_device *rdev = ddev->dev_private;
361 int cp = rdev->pm.profile;
375 struct radeon_device *rdev = ddev->dev_private;
378 if ((rdev->flags & RADEON_IS_PX) &&
382 mutex_lock(&rdev->pm.mutex);
383 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
385 rdev->pm.profile = PM_PROFILE_DEFAULT;
387 rdev->pm.profile = PM_PROFILE_AUTO;
389 rdev->pm.profile = PM_PROFILE_LOW;
391 rdev->pm.profile = PM_PROFILE_MID;
393 rdev->pm.profile = PM_PROFILE_HIGH;
398 radeon_pm_update_profile(rdev);
399 radeon_pm_set_clocks(rdev);
404 mutex_unlock(&rdev->pm.mutex);
414 struct radeon_device *rdev = ddev->dev_private;
415 int pm = rdev->pm.pm_method;
427 struct radeon_device *rdev = ddev->dev_private;
430 if ((rdev->flags & RADEON_IS_PX) &&
437 if (rdev->pm.pm_method == PM_METHOD_DPM) {
443 mutex_lock(&rdev->pm.mutex);
444 rdev->pm.pm_method = PM_METHOD_DYNPM;
445 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
446 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
447 mutex_unlock(&rdev->pm.mutex);
449 mutex_lock(&rdev->pm.mutex);
451 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
452 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
453 rdev->pm.pm_method = PM_METHOD_PROFILE;
454 mutex_unlock(&rdev->pm.mutex);
455 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
460 radeon_pm_compute_clocks(rdev);
470 struct radeon_device *rdev = ddev->dev_private;
471 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
484 struct radeon_device *rdev = ddev->dev_private;
486 mutex_lock(&rdev->pm.mutex);
488 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
490 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
492 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
494 mutex_unlock(&rdev->pm.mutex);
498 mutex_unlock(&rdev->pm.mutex);
501 if (!(rdev->flags & RADEON_IS_PX) ||
503 radeon_pm_compute_clocks(rdev);
514 struct radeon_device *rdev = ddev->dev_private;
515 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
517 if ((rdev->flags & RADEON_IS_PX) &&
532 struct radeon_device *rdev = ddev->dev_private;
537 if ((rdev->flags & RADEON_IS_PX) &&
541 mutex_lock(&rdev->pm.mutex);
552 if (rdev->asic->dpm.force_performance_level) {
553 if (rdev->pm.dpm.thermal_active) {
557 ret = radeon_dpm_force_performance_level(rdev, level);
562 mutex_unlock(&rdev->pm.mutex);
571 struct radeon_device *rdev = dev_get_drvdata(dev);
574 if (rdev->asic->dpm.fan_ctrl_get_mode)
575 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev);
586 struct radeon_device *rdev = dev_get_drvdata(dev);
590 if(!rdev->asic->dpm.fan_ctrl_set_mode)
599 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC);
602 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0);
627 struct radeon_device *rdev = dev_get_drvdata(dev);
637 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value);
648 struct radeon_device *rdev = dev_get_drvdata(dev);
652 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed);
672 struct radeon_device *rdev = dev_get_drvdata(dev);
673 struct drm_device *ddev = rdev->ddev;
677 if ((rdev->flags & RADEON_IS_PX) &&
681 if (rdev->asic->pm.get_temperature)
682 temp = radeon_get_temperature(rdev);
693 struct radeon_device *rdev = dev_get_drvdata(dev);
698 temp = rdev->pm.dpm.thermal.min_temp;
700 temp = rdev->pm.dpm.thermal.max_temp;
716 struct radeon_device *rdev = dev_get_drvdata(dev);
717 struct drm_device *ddev = rdev->ddev;
721 if ((rdev->flags & RADEON_IS_PX) &&
725 if (rdev->asic->dpm.get_current_sclk)
726 sclk = radeon_dpm_get_current_sclk(rdev);
741 struct radeon_device *rdev = dev_get_drvdata(dev);
742 struct drm_device *ddev = rdev->ddev;
746 if ((rdev->flags & RADEON_IS_PX) &&
750 if (rdev->asic->dpm.get_current_vddc)
751 vddc = rdev->asic->dpm.get_current_vddc(rdev);
776 struct radeon_device *rdev = dev_get_drvdata(dev);
780 if (rdev->pm.pm_method != PM_METHOD_DPM &&
793 !rdev->asic->dpm.get_current_vddc)
797 if (rdev->pm.no_fan &&
805 if ((!rdev->asic->dpm.get_fan_speed_percent &&
807 (!rdev->asic->dpm.fan_ctrl_get_mode &&
811 if ((!rdev->asic->dpm.set_fan_speed_percent &&
813 (!rdev->asic->dpm.fan_ctrl_set_mode &&
818 if ((!rdev->asic->dpm.set_fan_speed_percent &&
819 !rdev->asic->dpm.get_fan_speed_percent) &&
837 static int radeon_hwmon_init(struct radeon_device *rdev)
841 switch (rdev->pm.int_thermal_type) {
850 if (rdev->asic->pm.get_temperature == NULL)
852 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
853 "radeon", rdev,
855 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
856 err = PTR_ERR(rdev->pm.int_hwmon_dev);
857 dev_err(rdev->dev,
868 static void radeon_hwmon_fini(struct radeon_device *rdev)
870 if (rdev->pm.int_hwmon_dev)
871 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
876 struct radeon_device *rdev =
882 if (!rdev->pm.dpm_enabled)
885 if (rdev->asic->pm.get_temperature) {
886 int temp = radeon_get_temperature(rdev);
888 if (temp < rdev->pm.dpm.thermal.min_temp)
890 dpm_state = rdev->pm.dpm.user_state;
892 if (rdev->pm.dpm.thermal.high_to_low)
894 dpm_state = rdev->pm.dpm.user_state;
896 mutex_lock(&rdev->pm.mutex);
898 rdev->pm.dpm.thermal_active = true;
900 rdev->pm.dpm.thermal_active = false;
901 rdev->pm.dpm.state = dpm_state;
902 mutex_unlock(&rdev->pm.mutex);
904 radeon_pm_compute_clocks(rdev);
907 static bool radeon_dpm_single_display(struct radeon_device *rdev)
909 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
913 if (single_display && rdev->asic->dpm.vblank_too_short) {
914 if (radeon_dpm_vblank_too_short(rdev))
921 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120))
927 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
933 bool single_display = radeon_dpm_single_display(rdev);
946 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
947 ps = &rdev->pm.dpm.ps[i];
980 if (rdev->pm.dpm.uvd_ps)
981 return rdev->pm.dpm.uvd_ps;
1001 return rdev->pm.dpm.boot_ps;
1030 if (rdev->pm.dpm.uvd_ps) {
1031 return rdev->pm.dpm.uvd_ps;
1054 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
1060 bool single_display = radeon_dpm_single_display(rdev);
1063 if (!rdev->pm.dpm_enabled)
1066 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
1068 if ((!rdev->pm.dpm.thermal_active) &&
1069 (!rdev->pm.dpm.uvd_active))
1070 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
1072 dpm_state = rdev->pm.dpm.state;
1074 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
1076 rdev->pm.dpm.requested_ps = ps;
1081 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
1083 if (ps->vce_active != rdev->pm.dpm.vce_active)
1086 if (rdev->pm.dpm.single_display != single_display)
1088 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
1092 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
1094 radeon_bandwidth_update(rdev);
1096 radeon_dpm_display_configuration_changed(rdev);
1097 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1098 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1106 if (rdev->pm.dpm.new_active_crtcs ==
1107 rdev->pm.dpm.current_active_crtcs) {
1110 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
1111 (rdev->pm.dpm.new_active_crtc_count > 1)) {
1113 radeon_bandwidth_update(rdev);
1115 radeon_dpm_display_configuration_changed(rdev);
1116 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1117 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1127 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
1129 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
1132 down_write(&rdev->pm.mclk_lock);
1133 mutex_lock(&rdev->ring_lock);
1136 ps->vce_active = rdev->pm.dpm.vce_active;
1138 ret = radeon_dpm_pre_set_power_state(rdev);
1143 radeon_bandwidth_update(rdev);
1145 radeon_dpm_display_configuration_changed(rdev);
1149 struct radeon_ring *ring = &rdev->ring[i];
1151 radeon_fence_wait_empty(rdev, i);
1155 radeon_dpm_set_power_state(rdev);
1158 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
1160 radeon_dpm_post_set_power_state(rdev);
1162 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1163 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1164 rdev->pm.dpm.single_display = single_display;
1166 if (rdev->asic->dpm.force_performance_level) {
1167 if (rdev->pm.dpm.thermal_active) {
1168 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
1170 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
1172 rdev->pm.dpm.forced_level = level;
1175 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
1180 mutex_unlock(&rdev->ring_lock);
1181 up_write(&rdev->pm.mclk_lock);
1184 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
1188 if (rdev->asic->dpm.powergate_uvd) {
1189 mutex_lock(&rdev->pm.mutex);
1192 enable |= rdev->pm.dpm.sd > 0;
1193 enable |= rdev->pm.dpm.hd > 0;
1195 radeon_dpm_powergate_uvd(rdev, !enable);
1196 mutex_unlock(&rdev->pm.mutex);
1199 mutex_lock(&rdev->pm.mutex);
1200 rdev->pm.dpm.uvd_active = true;
1203 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
1205 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
1207 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
1209 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
1214 rdev->pm.dpm.state = dpm_state;
1215 mutex_unlock(&rdev->pm.mutex);
1217 mutex_lock(&rdev->pm.mutex);
1218 rdev->pm.dpm.uvd_active = false;
1219 mutex_unlock(&rdev->pm.mutex);
1222 radeon_pm_compute_clocks(rdev);
1226 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
1229 mutex_lock(&rdev->pm.mutex);
1230 rdev->pm.dpm.vce_active = true;
1232 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
1233 mutex_unlock(&rdev->pm.mutex);
1235 mutex_lock(&rdev->pm.mutex);
1236 rdev->pm.dpm.vce_active = false;
1237 mutex_unlock(&rdev->pm.mutex);
1240 radeon_pm_compute_clocks(rdev);
1243 static void radeon_pm_suspend_old(struct radeon_device *rdev)
1245 mutex_lock(&rdev->pm.mutex);
1246 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1247 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
1248 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
1250 mutex_unlock(&rdev->pm.mutex);
1252 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1255 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
1257 mutex_lock(&rdev->pm.mutex);
1259 radeon_dpm_disable(rdev);
1261 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1262 rdev->pm.dpm_enabled = false;
1263 mutex_unlock(&rdev->pm.mutex);
1266 void radeon_pm_suspend(struct radeon_device *rdev)
1268 if (rdev->pm.pm_method == PM_METHOD_DPM)
1269 radeon_pm_suspend_dpm(rdev);
1271 radeon_pm_suspend_old(rdev);
1274 static void radeon_pm_resume_old(struct radeon_device *rdev)
1277 if ((rdev->family >= CHIP_BARTS) &&
1278 (rdev->family <= CHIP_CAYMAN) &&
1279 rdev->mc_fw) {
1280 if (rdev->pm.default_vddc)
1281 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1283 if (rdev->pm.default_vddci)
1284 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1286 if (rdev->pm.default_sclk)
1287 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1288 if (rdev->pm.default_mclk)
1289 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1292 mutex_lock(&rdev->pm.mutex);
1293 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1294 rdev->pm.current_clock_mode_index = 0;
1295 rdev->pm.current_sclk = rdev->pm.default_sclk;
1296 rdev->pm.current_mclk = rdev->pm.default_mclk;
1297 if (rdev->pm.power_state) {
1298 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1299 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1301 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1302 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1303 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1304 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1307 mutex_unlock(&rdev->pm.mutex);
1308 radeon_pm_compute_clocks(rdev);
1311 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1316 mutex_lock(&rdev->pm.mutex);
1317 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1318 radeon_dpm_setup_asic(rdev);
1319 ret = radeon_dpm_enable(rdev);
1320 mutex_unlock(&rdev->pm.mutex);
1323 rdev->pm.dpm_enabled = true;
1328 if ((rdev->family >= CHIP_BARTS) &&
1329 (rdev->family <= CHIP_CAYMAN) &&
1330 rdev->mc_fw) {
1331 if (rdev->pm.default_vddc)
1332 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1334 if (rdev->pm.default_vddci)
1335 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1337 if (rdev->pm.default_sclk)
1338 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1339 if (rdev->pm.default_mclk)
1340 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1344 void radeon_pm_resume(struct radeon_device *rdev)
1346 if (rdev->pm.pm_method == PM_METHOD_DPM)
1347 radeon_pm_resume_dpm(rdev);
1349 radeon_pm_resume_old(rdev);
1352 static int radeon_pm_init_old(struct radeon_device *rdev)
1356 rdev->pm.profile = PM_PROFILE_DEFAULT;
1357 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1358 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1359 rdev->pm.dynpm_can_upclock = true;
1360 rdev->pm.dynpm_can_downclock = true;
1361 rdev->pm.default_sclk = rdev->clock.default_sclk;
1362 rdev->pm.default_mclk = rdev->clock.default_mclk;
1363 rdev->pm.current_sclk = rdev->clock.default_sclk;
1364 rdev->pm.current_mclk = rdev->clock.default_mclk;
1365 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1367 if (rdev->bios) {
1368 if (rdev->is_atom_bios)
1369 radeon_atombios_get_power_modes(rdev);
1371 radeon_combios_get_power_modes(rdev);
1372 radeon_pm_print_states(rdev);
1373 radeon_pm_init_profile(rdev);
1375 if ((rdev->family >= CHIP_BARTS) &&
1376 (rdev->family <= CHIP_CAYMAN) &&
1377 rdev->mc_fw) {
1378 if (rdev->pm.default_vddc)
1379 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1381 if (rdev->pm.default_vddci)
1382 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1384 if (rdev->pm.default_sclk)
1385 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1386 if (rdev->pm.default_mclk)
1387 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1392 ret = radeon_hwmon_init(rdev);
1396 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1398 if (rdev->pm.num_power_states > 1) {
1399 radeon_debugfs_pm_init(rdev);
1406 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1410 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1412 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1416 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1421 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1422 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1423 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1424 rdev->pm.default_sclk = rdev->clock.default_sclk;
1425 rdev->pm.default_mclk = rdev->clock.default_mclk;
1426 rdev->pm.current_sclk = rdev->clock.default_sclk;
1427 rdev->pm.current_mclk = rdev->clock.default_mclk;
1428 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1430 if (rdev->bios && rdev->is_atom_bios)
1431 radeon_atombios_get_power_modes(rdev);
1436 ret = radeon_hwmon_init(rdev);
1440 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1441 mutex_lock(&rdev->pm.mutex);
1442 radeon_dpm_init(rdev);
1443 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1445 radeon_dpm_print_power_states(rdev);
1446 radeon_dpm_setup_asic(rdev);
1447 ret = radeon_dpm_enable(rdev);
1448 mutex_unlock(&rdev->pm.mutex);
1451 rdev->pm.dpm_enabled = true;
1453 radeon_debugfs_pm_init(rdev);
1460 rdev->pm.dpm_enabled = false;
1461 if ((rdev->family >= CHIP_BARTS) &&
1462 (rdev->family <= CHIP_CAYMAN) &&
1463 rdev->mc_fw) {
1464 if (rdev->pm.default_vddc)
1465 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1467 if (rdev->pm.default_vddci)
1468 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1470 if (rdev->pm.default_sclk)
1471 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1472 if (rdev->pm.default_mclk)
1473 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1495 int radeon_pm_init(struct radeon_device *rdev)
1502 if (rdev->pdev->vendor == p->chip_vendor &&
1503 rdev->pdev->device == p->chip_device &&
1504 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
1505 rdev->pdev->subsystem_device == p->subsys_device) {
1513 switch (rdev->family) {
1523 if (!rdev->rlc_fw)
1524 rdev->pm.pm_method = PM_METHOD_PROFILE;
1525 else if ((rdev->family >= CHIP_RV770) &&
1526 (!(rdev->flags & RADEON_IS_IGP)) &&
1527 (!rdev->smc_fw))
1528 rdev->pm.pm_method = PM_METHOD_PROFILE;
1530 rdev->pm.pm_method = PM_METHOD_DPM;
1532 rdev->pm.pm_method = PM_METHOD_PROFILE;
1561 if (!rdev->rlc_fw)
1562 rdev->pm.pm_method = PM_METHOD_PROFILE;
1563 else if ((rdev->family >= CHIP_RV770) &&
1564 (!(rdev->flags & RADEON_IS_IGP)) &&
1565 (!rdev->smc_fw))
1566 rdev->pm.pm_method = PM_METHOD_PROFILE;
1568 rdev->pm.pm_method = PM_METHOD_PROFILE;
1570 rdev->pm.pm_method = PM_METHOD_PROFILE;
1572 rdev->pm.pm_method = PM_METHOD_DPM;
1576 rdev->pm.pm_method = PM_METHOD_PROFILE;
1580 if (rdev->pm.pm_method == PM_METHOD_DPM)
1581 return radeon_pm_init_dpm(rdev);
1583 return radeon_pm_init_old(rdev);
1586 int radeon_pm_late_init(struct radeon_device *rdev)
1590 if (rdev->pm.pm_method == PM_METHOD_DPM) {
1591 if (rdev->pm.dpm_enabled) {
1592 if (!rdev->pm.sysfs_initialized) {
1593 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1596 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1600 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1603 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1606 rdev->pm.sysfs_initialized = true;
1609 mutex_lock(&rdev->pm.mutex);
1610 ret = radeon_dpm_late_enable(rdev);
1611 mutex_unlock(&rdev->pm.mutex);
1613 rdev->pm.dpm_enabled = false;
1619 radeon_pm_compute_clocks(rdev);
1623 if ((rdev->pm.num_power_states > 1) &&
1624 (!rdev->pm.sysfs_initialized)) {
1626 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1629 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1633 rdev->pm.sysfs_initialized = true;
1639 static void radeon_pm_fini_old(struct radeon_device *rdev)
1641 if (rdev->pm.num_power_states > 1) {
1642 mutex_lock(&rdev->pm.mutex);
1643 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1644 rdev->pm.profile = PM_PROFILE_DEFAULT;
1645 radeon_pm_update_profile(rdev);
1646 radeon_pm_set_clocks(rdev);
1647 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1649 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1650 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1651 radeon_pm_set_clocks(rdev);
1653 mutex_unlock(&rdev->pm.mutex);
1655 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1657 device_remove_file(rdev->dev, &dev_attr_power_profile);
1658 device_remove_file(rdev->dev, &dev_attr_power_method);
1661 radeon_hwmon_fini(rdev);
1662 kfree(rdev->pm.power_state);
1665 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1667 if (rdev->pm.num_power_states > 1) {
1668 mutex_lock(&rdev->pm.mutex);
1669 radeon_dpm_disable(rdev);
1670 mutex_unlock(&rdev->pm.mutex);
1672 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1673 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1675 device_remove_file(rdev->dev, &dev_attr_power_profile);
1676 device_remove_file(rdev->dev, &dev_attr_power_method);
1678 radeon_dpm_fini(rdev);
1680 radeon_hwmon_fini(rdev);
1681 kfree(rdev->pm.power_state);
1684 void radeon_pm_fini(struct radeon_device *rdev)
1686 if (rdev->pm.pm_method == PM_METHOD_DPM)
1687 radeon_pm_fini_dpm(rdev);
1689 radeon_pm_fini_old(rdev);
1692 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1694 struct drm_device *ddev = rdev->ddev;
1698 if (rdev->pm.num_power_states < 2)
1701 mutex_lock(&rdev->pm.mutex);
1703 rdev->pm.active_crtcs = 0;
1704 rdev->pm.active_crtc_count = 0;
1705 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1710 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1711 rdev->pm.active_crtc_count++;
1716 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1717 radeon_pm_update_profile(rdev);
1718 radeon_pm_set_clocks(rdev);
1719 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1720 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1721 if (rdev->pm.active_crtc_count > 1) {
1722 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1723 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1725 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1726 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1727 radeon_pm_get_dynpm_state(rdev);
1728 radeon_pm_set_clocks(rdev);
1732 } else if (rdev->pm.active_crtc_count == 1) {
1735 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1736 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1737 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1738 radeon_pm_get_dynpm_state(rdev);
1739 radeon_pm_set_clocks(rdev);
1741 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1743 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1744 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1745 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1750 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1751 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1753 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1754 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1755 radeon_pm_get_dynpm_state(rdev);
1756 radeon_pm_set_clocks(rdev);
1762 mutex_unlock(&rdev->pm.mutex);
1765 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1767 struct drm_device *ddev = rdev->ddev;
1772 if (!rdev->pm.dpm_enabled)
1775 mutex_lock(&rdev->pm.mutex);
1778 rdev->pm.dpm.new_active_crtcs = 0;
1779 rdev->pm.dpm.new_active_crtc_count = 0;
1780 rdev->pm.dpm.high_pixelclock_count = 0;
1781 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1786 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1787 rdev->pm.dpm.new_active_crtc_count++;
1793 rdev->pm.dpm.high_pixelclock_count++;
1800 rdev->pm.dpm.ac_power = true;
1802 rdev->pm.dpm.ac_power = false;
1804 radeon_dpm_change_power_state_locked(rdev);
1806 mutex_unlock(&rdev->pm.mutex);
1810 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1812 if (rdev->pm.pm_method == PM_METHOD_DPM)
1813 radeon_pm_compute_clocks_dpm(rdev);
1815 radeon_pm_compute_clocks_old(rdev);
1818 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1826 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1827 if (rdev->pm.active_crtcs & (1 << crtc)) {
1828 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev,
1832 &rdev->mode_info.crtcs[crtc]->base.hwmode);
1842 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1845 bool in_vbl = radeon_pm_in_vbl(rdev);
1855 struct radeon_device *rdev;
1857 rdev = container_of(work, struct radeon_device,
1860 mutex_lock(&rdev->pm.mutex);
1861 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1866 struct radeon_ring *ring = &rdev->ring[i];
1869 not_processed += radeon_fence_count_emitted(rdev, i);
1876 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1877 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1878 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1879 rdev->pm.dynpm_can_upclock) {
1880 rdev->pm.dynpm_planned_action =
1882 rdev->pm.dynpm_action_timeout = jiffies +
1886 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1887 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1888 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1889 rdev->pm.dynpm_can_downclock) {
1890 rdev->pm.dynpm_planned_action =
1892 rdev->pm.dynpm_action_timeout = jiffies +
1900 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1901 time_after(jiffies, rdev->pm.dynpm_action_timeout)) {
1902 radeon_pm_get_dynpm_state(rdev);
1903 radeon_pm_set_clocks(rdev);
1906 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1909 mutex_unlock(&rdev->pm.mutex);
1919 struct radeon_device *rdev = m->private;
1920 struct drm_device *ddev = rdev->ddev;
1922 if ((rdev->flags & RADEON_IS_PX) &&
1925 } else if (rdev->pm.dpm_enabled) {
1926 mutex_lock(&rdev->pm.mutex);
1927 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1928 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1931 mutex_unlock(&rdev->pm.mutex);
1933 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1935 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1936 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1938 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1939 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1940 if (rdev->asic->pm.get_memory_clock)
1941 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1942 if (rdev->pm.current_vddc)
1943 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1944 if (rdev->asic->pm.get_pcie_lanes)
1945 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1954 static void radeon_debugfs_pm_init(struct radeon_device *rdev)
1957 struct dentry *root = rdev->ddev->primary->debugfs_root;
1959 debugfs_create_file("radeon_pm_info", 0444, root, rdev,