Lines Matching defs:value
197 * @value: value
204 uint32_t *value)
209 if (*value == 1) {
213 } else if (*value == 0) {
218 *value = *owner == applier ? 1 : 0;
242 uint32_t *value, value_tmp, *value_ptr, value_size;
248 value_ptr = (uint32_t *)((unsigned long)info->value);
249 value = &value_tmp;
254 *value = to_pci_dev(dev->dev)->device;
257 *value = rdev->num_gb_pipes;
260 *value = rdev->num_z_pipes;
265 *value = false;
267 *value = rdev->accel_working;
270 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
276 if (crtc && crtc->base.id == *value) {
278 *value = radeon_crtc->crtc_id;
284 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
292 *value = 3;
294 *value = 2;
296 *value = 0;
299 *value = rdev->accel_working;
304 *value = rdev->config.cik.tile_config;
306 *value = rdev->config.si.tile_config;
308 *value = rdev->config.cayman.tile_config;
310 *value = rdev->config.evergreen.tile_config;
312 *value = rdev->config.rv770.tile_config;
314 *value = rdev->config.r600.tile_config;
321 /* The "value" here is both an input and output parameter.
322 * If the input value is 1, filp requests hyper-z access.
323 * If the input value is 0, filp revokes its hyper-z access.
325 * When returning, the value is 1 if filp owns hyper-z access,
327 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
331 if (*value >= 2) {
332 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
335 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
339 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
343 if (*value >= 2) {
344 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
347 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
350 /* return clock value in KHz */
352 *value = radeon_get_xclk(rdev) * 10;
354 *value = rdev->clock.spll.reference_freq * 10;
358 *value = rdev->config.cik.max_backends_per_se *
361 *value = rdev->config.si.max_backends_per_se *
364 *value = rdev->config.cayman.max_backends_per_se *
367 *value = rdev->config.evergreen.max_backends;
369 *value = rdev->config.rv770.max_backends;
371 *value = rdev->config.r600.max_backends;
378 *value = rdev->config.cik.max_tile_pipes;
380 *value = rdev->config.si.max_tile_pipes;
382 *value = rdev->config.cayman.max_tile_pipes;
384 *value = rdev->config.evergreen.max_tile_pipes;
386 *value = rdev->config.rv770.max_tile_pipes;
388 *value = rdev->config.r600.max_tile_pipes;
394 *value = 1;
398 *value = rdev->config.cik.backend_map;
400 *value = rdev->config.si.backend_map;
402 *value = rdev->config.cayman.backend_map;
404 *value = rdev->config.evergreen.backend_map;
406 *value = rdev->config.rv770.backend_map;
408 *value = rdev->config.r600.backend_map;
417 *value = RADEON_VA_RESERVED_SIZE;
423 *value = RADEON_IB_VM_MAX_SIZE;
427 *value = rdev->config.cik.max_cu_per_sh;
429 *value = rdev->config.si.max_cu_per_sh;
431 *value = rdev->config.cayman.max_pipes_per_simd;
433 *value = rdev->config.evergreen.max_pipes;
435 *value = rdev->config.rv770.max_pipes;
437 *value = rdev->config.r600.max_pipes;
447 value = (uint32_t *)&value64;
453 *value = rdev->config.cik.max_shader_engines;
455 *value = rdev->config.si.max_shader_engines;
457 *value = rdev->config.cayman.max_shader_engines;
459 *value = rdev->config.evergreen.num_ses;
461 *value = 1;
465 *value = rdev->config.cik.max_sh_per_se;
467 *value = rdev->config.si.max_sh_per_se;
472 *value = rdev->fastfb_working;
475 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
479 switch (*value) {
482 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
485 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
486 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
489 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
492 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
500 value = rdev->config.cik.tile_mode_array;
503 value = rdev->config.si.tile_mode_array;
512 value = rdev->config.cik.macrotile_mode_array;
520 *value = 1;
524 *value = rdev->config.cik.backend_enable_mask;
526 *value = rdev->config.si.backend_enable_mask;
535 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
537 *value = rdev->pm.default_sclk * 10;
540 *value = rdev->vce.fw_version;
543 *value = rdev->vce.fb_version;
546 value = (uint32_t *)&value64;
551 value = (uint32_t *)&value64;
557 value = (uint32_t *)&value64;
564 *value = rdev->config.cik.active_cus;
566 *value = rdev->config.si.active_cus;
568 *value = rdev->config.cayman.active_simds;
570 *value = rdev->config.evergreen.active_simds;
572 *value = rdev->config.rv770.active_simds;
574 *value = rdev->config.r600.active_simds;
576 *value = 1;
581 *value = radeon_get_temperature(rdev);
583 *value = 0;
588 *value = radeon_dpm_get_current_sclk(rdev) / 100;
590 *value = rdev->pm.current_sclk / 100;
595 *value = radeon_dpm_get_current_mclk(rdev) / 100;
597 *value = rdev->pm.current_mclk / 100;
600 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
604 if (radeon_get_allowed_info_register(rdev, *value, value))
608 *value = true;
611 *value = atomic_read(&rdev->gpu_reset_counter);
617 if (copy_to_user(value_ptr, (char *)value, value_size)) {
815 /* Fallback to use value as is. */