Lines Matching defs:rdev
63 struct radeon_device *rdev = dev->dev_private;
65 if (rdev == NULL)
68 if (rdev->rmmio == NULL)
76 radeon_acpi_fini(rdev);
78 radeon_modeset_fini(rdev);
79 radeon_device_fini(rdev);
81 if (rdev->agp)
82 arch_phys_wc_del(rdev->agp->agp_mtrr);
83 kfree(rdev->agp);
84 rdev->agp = NULL;
87 kfree(rdev);
107 struct radeon_device *rdev;
110 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
111 if (rdev == NULL) {
114 dev->dev_private = (void *)rdev;
117 rdev->hose = pdev->sysdata;
121 rdev->agp = radeon_agp_head_init(dev);
122 if (rdev->agp) {
123 rdev->agp->agp_mtrr = arch_phys_wc_add(
124 rdev->agp->agp_info.aper_base,
125 rdev->agp->agp_info.aper_size *
150 r = radeon_device_init(rdev, dev, pdev, flags);
160 r = radeon_modeset_init(rdev);
168 acpi_status = radeon_acpi_init(rdev);
206 struct radeon_device *rdev = dev->dev_private;
208 mutex_lock(&rdev->gem.mutex);
219 mutex_unlock(&rdev->gem.mutex);
239 struct radeon_device *rdev = dev->dev_private;
241 struct radeon_mode_info *minfo = &rdev->mode_info;
257 *value = rdev->num_gb_pipes;
260 *value = rdev->num_z_pipes;
264 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
267 *value = rdev->accel_working;
274 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
289 if (rdev->family == CHIP_HAWAII) {
290 if (rdev->accel_working) {
291 if (rdev->new_fw)
299 *value = rdev->accel_working;
303 if (rdev->family >= CHIP_BONAIRE)
304 *value = rdev->config.cik.tile_config;
305 else if (rdev->family >= CHIP_TAHITI)
306 *value = rdev->config.si.tile_config;
307 else if (rdev->family >= CHIP_CAYMAN)
308 *value = rdev->config.cayman.tile_config;
309 else if (rdev->family >= CHIP_CEDAR)
310 *value = rdev->config.evergreen.tile_config;
311 else if (rdev->family >= CHIP_RV770)
312 *value = rdev->config.rv770.tile_config;
313 else if (rdev->family >= CHIP_R600)
314 *value = rdev->config.r600.tile_config;
335 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
347 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
351 if (rdev->asic->get_xclk)
352 *value = radeon_get_xclk(rdev) * 10;
354 *value = rdev->clock.spll.reference_freq * 10;
357 if (rdev->family >= CHIP_BONAIRE)
358 *value = rdev->config.cik.max_backends_per_se *
359 rdev->config.cik.max_shader_engines;
360 else if (rdev->family >= CHIP_TAHITI)
361 *value = rdev->config.si.max_backends_per_se *
362 rdev->config.si.max_shader_engines;
363 else if (rdev->family >= CHIP_CAYMAN)
364 *value = rdev->config.cayman.max_backends_per_se *
365 rdev->config.cayman.max_shader_engines;
366 else if (rdev->family >= CHIP_CEDAR)
367 *value = rdev->config.evergreen.max_backends;
368 else if (rdev->family >= CHIP_RV770)
369 *value = rdev->config.rv770.max_backends;
370 else if (rdev->family >= CHIP_R600)
371 *value = rdev->config.r600.max_backends;
377 if (rdev->family >= CHIP_BONAIRE)
378 *value = rdev->config.cik.max_tile_pipes;
379 else if (rdev->family >= CHIP_TAHITI)
380 *value = rdev->config.si.max_tile_pipes;
381 else if (rdev->family >= CHIP_CAYMAN)
382 *value = rdev->config.cayman.max_tile_pipes;
383 else if (rdev->family >= CHIP_CEDAR)
384 *value = rdev->config.evergreen.max_tile_pipes;
385 else if (rdev->family >= CHIP_RV770)
386 *value = rdev->config.rv770.max_tile_pipes;
387 else if (rdev->family >= CHIP_R600)
388 *value = rdev->config.r600.max_tile_pipes;
397 if (rdev->family >= CHIP_BONAIRE)
398 *value = rdev->config.cik.backend_map;
399 else if (rdev->family >= CHIP_TAHITI)
400 *value = rdev->config.si.backend_map;
401 else if (rdev->family >= CHIP_CAYMAN)
402 *value = rdev->config.cayman.backend_map;
403 else if (rdev->family >= CHIP_CEDAR)
404 *value = rdev->config.evergreen.backend_map;
405 else if (rdev->family >= CHIP_RV770)
406 *value = rdev->config.rv770.backend_map;
407 else if (rdev->family >= CHIP_R600)
408 *value = rdev->config.r600.backend_map;
415 if (rdev->family < CHIP_CAYMAN)
421 if (rdev->family < CHIP_CAYMAN)
426 if (rdev->family >= CHIP_BONAIRE)
427 *value = rdev->config.cik.max_cu_per_sh;
428 else if (rdev->family >= CHIP_TAHITI)
429 *value = rdev->config.si.max_cu_per_sh;
430 else if (rdev->family >= CHIP_CAYMAN)
431 *value = rdev->config.cayman.max_pipes_per_simd;
432 else if (rdev->family >= CHIP_CEDAR)
433 *value = rdev->config.evergreen.max_pipes;
434 else if (rdev->family >= CHIP_RV770)
435 *value = rdev->config.rv770.max_pipes;
436 else if (rdev->family >= CHIP_R600)
437 *value = rdev->config.r600.max_pipes;
443 if (rdev->family < CHIP_R600) {
449 value64 = radeon_get_gpu_clock_counter(rdev);
452 if (rdev->family >= CHIP_BONAIRE)
453 *value = rdev->config.cik.max_shader_engines;
454 else if (rdev->family >= CHIP_TAHITI)
455 *value = rdev->config.si.max_shader_engines;
456 else if (rdev->family >= CHIP_CAYMAN)
457 *value = rdev->config.cayman.max_shader_engines;
458 else if (rdev->family >= CHIP_CEDAR)
459 *value = rdev->config.evergreen.num_ses;
464 if (rdev->family >= CHIP_BONAIRE)
465 *value = rdev->config.cik.max_sh_per_se;
466 else if (rdev->family >= CHIP_TAHITI)
467 *value = rdev->config.si.max_sh_per_se;
472 *value = rdev->fastfb_working;
482 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
485 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
486 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
489 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
492 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
499 if (rdev->family >= CHIP_BONAIRE) {
500 value = rdev->config.cik.tile_mode_array;
502 } else if (rdev->family >= CHIP_TAHITI) {
503 value = rdev->config.si.tile_mode_array;
511 if (rdev->family >= CHIP_BONAIRE) {
512 value = rdev->config.cik.macrotile_mode_array;
523 if (rdev->family >= CHIP_BONAIRE) {
524 *value = rdev->config.cik.backend_enable_mask;
525 } else if (rdev->family >= CHIP_TAHITI) {
526 *value = rdev->config.si.backend_enable_mask;
533 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
534 rdev->pm.dpm_enabled)
535 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
537 *value = rdev->pm.default_sclk * 10;
540 *value = rdev->vce.fw_version;
543 *value = rdev->vce.fb_version;
548 value64 = atomic64_read(&rdev->num_bytes_moved);
553 man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM);
559 man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_TT);
563 if (rdev->family >= CHIP_BONAIRE)
564 *value = rdev->config.cik.active_cus;
565 else if (rdev->family >= CHIP_TAHITI)
566 *value = rdev->config.si.active_cus;
567 else if (rdev->family >= CHIP_CAYMAN)
568 *value = rdev->config.cayman.active_simds;
569 else if (rdev->family >= CHIP_CEDAR)
570 *value = rdev->config.evergreen.active_simds;
571 else if (rdev->family >= CHIP_RV770)
572 *value = rdev->config.rv770.active_simds;
573 else if (rdev->family >= CHIP_R600)
574 *value = rdev->config.r600.active_simds;
580 if (rdev->asic->pm.get_temperature)
581 *value = radeon_get_temperature(rdev);
587 if (rdev->pm.dpm_enabled)
588 *value = radeon_dpm_get_current_sclk(rdev) / 100;
590 *value = rdev->pm.current_sclk / 100;
594 if (rdev->pm.dpm_enabled)
595 *value = radeon_dpm_get_current_mclk(rdev) / 100;
597 *value = rdev->pm.current_mclk / 100;
604 if (radeon_get_allowed_info_register(rdev, *value, value))
611 *value = atomic_read(&rdev->gpu_reset_counter);
635 struct radeon_device *rdev = dev->dev_private;
649 if (rdev->family >= CHIP_CAYMAN) {
657 if (rdev->accel_working) {
659 r = radeon_vm_init(rdev, vm);
663 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
669 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
670 rdev->ring_tmp_bo.bo);
676 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
691 radeon_vm_fini(rdev, vm);
713 struct radeon_device *rdev = dev->dev_private;
717 mutex_lock(&rdev->gem.mutex);
718 if (rdev->hyperz_filp == file_priv)
719 rdev->hyperz_filp = NULL;
720 if (rdev->cmask_filp == file_priv)
721 rdev->cmask_filp = NULL;
722 mutex_unlock(&rdev->gem.mutex);
724 radeon_uvd_free_handles(rdev, file_priv);
725 radeon_vce_free_handles(rdev, file_priv);
728 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
733 if (rdev->accel_working) {
734 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
737 radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
738 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
740 radeon_vm_fini(rdev, vm);
767 struct radeon_device *rdev = dev->dev_private;
769 if (pipe >= rdev->num_crtc) {
782 if (rdev->mode_info.crtcs[pipe]) {
787 count = radeon_get_vblank_counter(rdev, pipe);
795 &rdev->mode_info.crtcs[pipe]->base.hwmode);
796 } while (count != radeon_get_vblank_counter(rdev, pipe));
816 count = radeon_get_vblank_counter(rdev, pipe);
835 struct radeon_device *rdev = dev->dev_private;
839 if (pipe >= rdev->num_crtc) {
844 spin_lock_irqsave(&rdev->irq.lock, irqflags);
845 rdev->irq.crtc_vblank_int[pipe] = true;
846 r = radeon_irq_set(rdev);
847 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
862 struct radeon_device *rdev = dev->dev_private;
865 if (pipe >= rdev->num_crtc) {
870 spin_lock_irqsave(&rdev->irq.lock, irqflags);
871 rdev->irq.crtc_vblank_int[pipe] = false;
872 radeon_irq_set(rdev);
873 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);