Lines Matching defs:tmp
331 u32 tmp, reg;
346 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
347 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
474 tmp = RREG32(i2c_cntl_0);
475 if (tmp & RADEON_I2C_GO)
477 tmp = RREG32(i2c_cntl_0);
478 if (tmp & RADEON_I2C_DONE)
481 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
482 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
506 tmp = RREG32(i2c_cntl_0);
507 if (tmp & RADEON_I2C_GO)
509 tmp = RREG32(i2c_cntl_0);
510 if (tmp & RADEON_I2C_DONE)
513 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
514 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
534 tmp = RREG32(i2c_cntl_0);
535 if (tmp & RADEON_I2C_GO)
537 tmp = RREG32(i2c_cntl_0);
538 if (tmp & RADEON_I2C_DONE)
541 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
542 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
560 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
561 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
562 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
583 u32 tmp, reg;
593 tmp = RREG32(rec->mask_clk_reg);
594 tmp &= ~rec->mask_clk_mask;
595 WREG32(rec->mask_clk_reg, tmp);
596 tmp = RREG32(rec->mask_clk_reg);
598 tmp = RREG32(rec->mask_data_reg);
599 tmp &= ~rec->mask_data_mask;
600 WREG32(rec->mask_data_reg, tmp);
601 tmp = RREG32(rec->mask_data_reg);
604 tmp = RREG32(rec->a_clk_reg);
605 tmp &= ~rec->a_clk_mask;
606 WREG32(rec->a_clk_reg, tmp);
607 tmp = RREG32(rec->a_clk_reg);
609 tmp = RREG32(rec->a_data_reg);
610 tmp &= ~rec->a_data_mask;
611 WREG32(rec->a_data_reg, tmp);
612 tmp = RREG32(rec->a_data_reg);
615 tmp = RREG32(rec->en_clk_reg);
616 tmp &= ~rec->en_clk_mask;
617 WREG32(rec->en_clk_reg, tmp);
618 tmp = RREG32(rec->en_clk_reg);
620 tmp = RREG32(rec->en_data_reg);
621 tmp &= ~rec->en_data_mask;
622 WREG32(rec->en_data_reg, tmp);
623 tmp = RREG32(rec->en_data_reg);
626 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
627 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
682 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
683 if (tmp & AVIVO_DC_I2C_GO)
685 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
686 if (tmp & AVIVO_DC_I2C_DONE)
689 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
724 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
725 if (tmp & AVIVO_DC_I2C_GO)
727 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
728 if (tmp & AVIVO_DC_I2C_DONE)
731 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
767 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
768 if (tmp & AVIVO_DC_I2C_GO)
770 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
771 if (tmp & AVIVO_DC_I2C_DONE)
774 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
797 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
798 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
799 WREG32(RADEON_BIOS_6_SCRATCH, tmp);