Lines Matching defs:rdev
53 struct radeon_device *rdev = dev->dev_private;
91 struct radeon_device *rdev = dev->dev_private;
125 struct radeon_device *rdev = dev->dev_private;
184 if (ASIC_IS_DCE8(rdev)) {
197 struct radeon_device *rdev = dev->dev_private;
224 struct radeon_device *rdev = dev->dev_private;
229 if (ASIC_IS_DCE5(rdev))
231 else if (ASIC_IS_DCE4(rdev))
233 else if (ASIC_IS_AVIVO(rdev))
282 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
284 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
302 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
305 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
311 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
315 update_pending = radeon_page_flip_pending(rdev, crtc_id);
337 radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
340 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
341 ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) {
350 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
352 radeon_crtc_handle_flip(rdev, crtc_id);
358 * @rdev: radeon device pointer
363 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
365 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
373 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
380 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
392 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
395 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
410 struct radeon_device *rdev = work->rdev;
411 struct drm_device *dev = rdev->ddev;
412 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
419 down_read(&rdev->exclusive_lock);
424 if (fence && fence->rdev == rdev) {
427 up_read(&rdev->exclusive_lock);
429 r = radeon_gpu_reset(rdev);
431 down_read(&rdev->exclusive_lock);
459 (!ASIC_IS_AVIVO(rdev) ||
468 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
471 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);
475 up_read(&rdev->exclusive_lock);
486 struct radeon_device *rdev = dev->dev_private;
503 work->rdev = rdev;
529 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
546 if (!ASIC_IS_AVIVO(rdev)) {
552 if (ASIC_IS_R300(rdev)) {
625 struct radeon_device *rdev;
649 rdev = dev->dev_private;
652 if (active && !rdev->have_disp_power_ref) {
653 rdev->have_disp_power_ref = true;
658 if (!active && rdev->have_disp_power_ref) {
660 rdev->have_disp_power_ref = false;
683 struct radeon_device *rdev = dev->dev_private;
700 rdev->mode_info.crtcs[index] = radeon_crtc;
702 if (rdev->family >= CHIP_BONAIRE) {
718 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
852 struct radeon_device *rdev = dev->dev_private;
855 if (rdev->bios) {
856 if (rdev->is_atom_bios) {
866 if (!ASIC_IS_AVIVO(rdev))
1404 static int radeon_modeset_create_props(struct radeon_device *rdev)
1408 if (rdev->is_atom_bios) {
1409 rdev->mode_info.coherent_mode_property =
1410 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1411 if (!rdev->mode_info.coherent_mode_property)
1415 if (!ASIC_IS_AVIVO(rdev)) {
1417 rdev->mode_info.tmds_pll_property =
1418 drm_property_create_enum(rdev->ddev, 0,
1423 rdev->mode_info.load_detect_property =
1424 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1425 if (!rdev->mode_info.load_detect_property)
1428 drm_mode_create_scaling_mode_property(rdev->ddev);
1431 rdev->mode_info.tv_std_property =
1432 drm_property_create_enum(rdev->ddev, 0,
1437 rdev->mode_info.underscan_property =
1438 drm_property_create_enum(rdev->ddev, 0,
1442 rdev->mode_info.underscan_hborder_property =
1443 drm_property_create_range(rdev->ddev, 0,
1445 if (!rdev->mode_info.underscan_hborder_property)
1448 rdev->mode_info.underscan_vborder_property =
1449 drm_property_create_range(rdev->ddev, 0,
1451 if (!rdev->mode_info.underscan_vborder_property)
1455 rdev->mode_info.audio_property =
1456 drm_property_create_enum(rdev->ddev, 0,
1461 rdev->mode_info.dither_property =
1462 drm_property_create_enum(rdev->ddev, 0,
1467 rdev->mode_info.output_csc_property =
1468 drm_property_create_enum(rdev->ddev, 0,
1475 void radeon_update_display_priority(struct radeon_device *rdev)
1485 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1486 !(rdev->flags & RADEON_IS_IGP))
1487 rdev->disp_priority = 2;
1489 rdev->disp_priority = 0;
1491 rdev->disp_priority = radeon_disp_priority;
1498 static void radeon_afmt_init(struct radeon_device *rdev)
1503 rdev->mode_info.afmt[i] = NULL;
1505 if (ASIC_IS_NODCE(rdev)) {
1507 } else if (ASIC_IS_DCE4(rdev)) {
1523 if (ASIC_IS_DCE8(rdev))
1525 else if (ASIC_IS_DCE6(rdev))
1527 else if (ASIC_IS_DCE5(rdev))
1529 else if (ASIC_IS_DCE41(rdev))
1536 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1537 if (rdev->mode_info.afmt[i]) {
1538 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1539 rdev->mode_info.afmt[i]->id = i;
1542 } else if (ASIC_IS_DCE3(rdev)) {
1544 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1545 if (rdev->mode_info.afmt[0]) {
1546 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1547 rdev->mode_info.afmt[0]->id = 0;
1549 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1550 if (rdev->mode_info.afmt[1]) {
1551 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1552 rdev->mode_info.afmt[1]->id = 1;
1554 } else if (ASIC_IS_DCE2(rdev)) {
1556 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1557 if (rdev->mode_info.afmt[0]) {
1558 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1559 rdev->mode_info.afmt[0]->id = 0;
1562 if (rdev->family >= CHIP_R600) {
1563 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1564 if (rdev->mode_info.afmt[1]) {
1565 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1566 rdev->mode_info.afmt[1]->id = 1;
1572 static void radeon_afmt_fini(struct radeon_device *rdev)
1577 kfree(rdev->mode_info.afmt[i]);
1578 rdev->mode_info.afmt[i] = NULL;
1582 int radeon_modeset_init(struct radeon_device *rdev)
1587 drm_mode_config_init(rdev->ddev);
1588 rdev->mode_info.mode_config_initialized = true;
1590 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1592 if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600)
1593 rdev->ddev->mode_config.async_page_flip = true;
1595 if (ASIC_IS_DCE5(rdev)) {
1596 rdev->ddev->mode_config.max_width = 16384;
1597 rdev->ddev->mode_config.max_height = 16384;
1598 } else if (ASIC_IS_AVIVO(rdev)) {
1599 rdev->ddev->mode_config.max_width = 8192;
1600 rdev->ddev->mode_config.max_height = 8192;
1602 rdev->ddev->mode_config.max_width = 4096;
1603 rdev->ddev->mode_config.max_height = 4096;
1606 rdev->ddev->mode_config.preferred_depth = 24;
1607 rdev->ddev->mode_config.prefer_shadow = 1;
1609 rdev->ddev->mode_config.fb_modifiers_not_supported = true;
1611 ret = radeon_modeset_create_props(rdev);
1617 radeon_i2c_init(rdev);
1620 if (!rdev->is_atom_bios) {
1622 radeon_combios_check_hardcoded_edid(rdev);
1626 for (i = 0; i < rdev->num_crtc; i++) {
1627 radeon_crtc_init(rdev->ddev, i);
1631 ret = radeon_setup_enc_conn(rdev->ddev);
1637 if (rdev->is_atom_bios) {
1638 radeon_atom_encoder_init(rdev);
1639 radeon_atom_disp_eng_pll_init(rdev);
1643 radeon_hpd_init(rdev);
1646 radeon_afmt_init(rdev);
1648 drm_kms_helper_poll_init(rdev->ddev);
1651 ret = radeon_pm_late_init(rdev);
1656 void radeon_modeset_fini(struct radeon_device *rdev)
1658 if (rdev->mode_info.mode_config_initialized) {
1659 drm_kms_helper_poll_fini(rdev->ddev);
1660 radeon_hpd_fini(rdev);
1661 drm_helper_force_disable_all(rdev->ddev);
1662 radeon_afmt_fini(rdev);
1663 drm_mode_config_cleanup(rdev->ddev);
1664 rdev->mode_info.mode_config_initialized = false;
1667 kfree(rdev->mode_info.bios_hardcoded_edid);
1670 radeon_i2c_fini(rdev);
1690 struct radeon_device *rdev = dev->dev_private;
1727 if (ASIC_IS_AVIVO(rdev) &&
1822 struct radeon_device *rdev = dev->dev_private;
1830 if (ASIC_IS_DCE4(rdev)) {
1873 } else if (ASIC_IS_AVIVO(rdev)) {
1952 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;