Lines Matching refs:lvds
1103 struct radeon_encoder_lvds *lvds;
1108 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1110 if (!lvds)
1117 lvds->panel_pwr_delay = 200;
1118 lvds->panel_vcc_delay = 2000;
1120 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1121 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1122 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1125 lvds->native_mode.vdisplay =
1129 lvds->native_mode.vdisplay =
1133 lvds->native_mode.hdisplay =
1137 lvds->native_mode.hdisplay =
1140 if ((lvds->native_mode.hdisplay < 640) ||
1141 (lvds->native_mode.vdisplay < 480)) {
1142 lvds->native_mode.hdisplay = 640;
1143 lvds->native_mode.vdisplay = 480;
1149 lvds->use_bios_dividers = false;
1151 lvds->panel_ref_divider =
1153 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1154 lvds->panel_fb_divider = ppll_val & 0x7ff;
1156 if ((lvds->panel_ref_divider != 0) &&
1157 (lvds->panel_fb_divider > 3))
1158 lvds->use_bios_dividers = true;
1160 lvds->panel_vcc_delay = 200;
1163 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1164 lvds->native_mode.vdisplay);
1166 return lvds;
1178 struct radeon_encoder_lvds *lvds = NULL;
1183 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1185 if (!lvds)
1194 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1195 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1197 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1198 lvds->native_mode.vdisplay);
1200 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1201 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1203 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1204 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1205 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1207 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1208 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1209 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1210 if ((lvds->panel_ref_divider != 0) &&
1211 (lvds->panel_fb_divider > 3))
1212 lvds->use_bios_dividers = true;
1215 lvds->lvds_gen_cntl = 0xff00;
1217 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1220 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1224 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1227 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1230 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1237 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1240 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1243 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1246 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1248 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1255 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1256 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1259 if (hss > lvds->native_mode.hdisplay)
1262 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1264 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1266 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1269 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1271 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1273 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1276 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1277 lvds->native_mode.flags = 0;
1279 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1285 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1288 if (lvds)
1289 encoder->native_mode = lvds->native_mode;
1290 return lvds;