Lines Matching refs:lvds
1622 struct radeon_encoder_atom_dig *lvds = NULL;
1629 lvds =
1632 if (!lvds)
1635 lvds->native_mode.clock =
1637 lvds->native_mode.hdisplay =
1639 lvds->native_mode.vdisplay =
1641 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1643 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1645 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1647 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1649 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1651 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1653 lvds->panel_pwr_delay =
1655 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1659 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1661 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1663 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1665 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1667 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1669 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1670 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1673 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1675 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1677 encoder->native_mode = lvds->native_mode;
1680 lvds->linkb = true;
1682 lvds->linkb = false;
1738 lvds->native_mode.width_mm = panel_res_record->usHSize;
1739 lvds->native_mode.height_mm = panel_res_record->usVSize;
1752 return lvds;