Lines Matching defs:rdev
46 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
51 if ((rdev->family == CHIP_R420) ||
52 (rdev->family == CHIP_R423) ||
53 (rdev->family == CHIP_RV410)) {
63 if (ASIC_IS_DCE4(rdev)) {
76 if (ASIC_IS_DCE3(rdev)) {
127 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
130 struct atom_context *ctx = rdev->mode_info.atom_context;
150 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
164 void radeon_atombios_i2c_init(struct radeon_device *rdev)
166 struct atom_context *ctx = rdev->mode_info.atom_context;
183 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
189 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
197 struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
200 struct atom_context *ctx = rdev->mode_info.atom_context;
235 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
243 if (ASIC_IS_DCE6(rdev))
245 else if (ASIC_IS_DCE4(rdev))
434 struct radeon_device *rdev = dev->dev_private;
435 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
518 struct radeon_device *rdev = dev->dev_private;
519 struct radeon_mode_info *mode_info = &rdev->mode_info;
582 if ((rdev->flags & RADEON_IS_IGP) &&
717 radeon_lookup_i2c_gpio(rdev,
779 ddc_bus = radeon_lookup_i2c_gpio(rdev,
787 gpio = radeon_atombios_lookup_gpio(rdev,
789 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
836 struct radeon_device *rdev = dev->dev_private;
838 if (rdev->flags & RADEON_IS_IGP) {
844 struct radeon_mode_info *mode_info = &rdev->mode_info;
887 struct radeon_device *rdev = dev->dev_private;
888 struct radeon_mode_info *mode_info = &rdev->mode_info;
965 radeon_lookup_i2c_gpio(rdev,
1007 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1103 static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev)
1105 struct radeon_mode_info *mode_info = &rdev->mode_info;
1115 rdev->clock.vco_freq =
1122 struct radeon_device *rdev = dev->dev_private;
1123 struct radeon_mode_info *mode_info = &rdev->mode_info;
1127 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1128 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1129 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1130 struct radeon_pll *spll = &rdev->clock.spll;
1131 struct radeon_pll *mpll = &rdev->clock.mpll;
1168 if (ASIC_IS_AVIVO(rdev))
1182 if (ASIC_IS_DCE4(rdev))
1197 if (ASIC_IS_AVIVO(rdev))
1209 if (ASIC_IS_DCE4(rdev))
1224 if (ASIC_IS_AVIVO(rdev))
1235 rdev->clock.default_sclk =
1237 rdev->clock.default_mclk =
1240 if (ASIC_IS_DCE4(rdev)) {
1241 rdev->clock.default_dispclk =
1243 if (rdev->clock.default_dispclk == 0) {
1244 if (ASIC_IS_DCE6(rdev))
1245 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1246 else if (ASIC_IS_DCE5(rdev))
1247 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1249 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1252 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1254 rdev->clock.default_dispclk / 100);
1255 rdev->clock.default_dispclk = 60000;
1257 rdev->clock.dp_extclk =
1259 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1263 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1264 if (rdev->clock.max_pixel_clock == 0)
1265 rdev->clock.max_pixel_clock = 40000;
1268 rdev->mode_info.firmware_flags =
1271 if (ASIC_IS_DCE8(rdev))
1272 rdev->clock.vco_freq =
1274 else if (ASIC_IS_DCE5(rdev))
1275 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1276 else if (ASIC_IS_DCE41(rdev))
1277 radeon_atombios_get_dentist_vco_freq(rdev);
1279 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1281 if (rdev->clock.vco_freq == 0)
1282 rdev->clock.vco_freq = 360000; /* 3.6 GHz */
1290 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1292 struct radeon_mode_info *mode_info = &rdev->mode_info;
1299 if (rdev->family == CHIP_RS600)
1327 struct radeon_device *rdev = dev->dev_private;
1328 struct radeon_mode_info *mode_info = &rdev->mode_info;
1372 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1376 struct radeon_mode_info *mode_info = &rdev->mode_info;
1412 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1416 struct radeon_mode_info *mode_info = &rdev->mode_info;
1500 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1504 struct radeon_mode_info *mode_info = &rdev->mode_info;
1513 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1517 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1589 if (rdev->flags & RADEON_IS_IGP)
1590 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1616 struct radeon_device *rdev = dev->dev_private;
1617 struct radeon_mode_info *mode_info = &rdev->mode_info;
1723 rdev->mode_info.bios_hardcoded_edid = edid;
1724 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1759 struct radeon_device *rdev = dev->dev_private;
1760 struct radeon_mode_info *mode_info = &rdev->mode_info;
1786 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1789 struct radeon_mode_info *mode_info = &rdev->mode_info;
1884 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1886 struct radeon_mode_info *mode_info = &rdev->mode_info;
1945 struct radeon_device *rdev = dev->dev_private;
1946 struct radeon_mode_info *mode_info = &rdev->mode_info;
1977 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
2038 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2042 rdev->pm.power_state[state_index].misc = misc;
2043 rdev->pm.power_state[state_index].misc2 = misc2;
2046 rdev->pm.power_state[state_index].type =
2049 rdev->pm.power_state[state_index].type =
2052 rdev->pm.power_state[state_index].type =
2055 rdev->pm.power_state[state_index].type =
2058 rdev->pm.power_state[state_index].type =
2060 rdev->pm.power_state[state_index].flags &=
2064 rdev->pm.power_state[state_index].type =
2067 rdev->pm.power_state[state_index].type =
2069 rdev->pm.default_power_state_index = state_index;
2070 rdev->pm.power_state[state_index].default_clock_mode =
2071 &rdev->pm.power_state[state_index].clock_info[0];
2073 rdev->pm.power_state[state_index].clock_info[0].flags |=
2078 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2080 struct radeon_mode_info *mode_info = &rdev->mode_info;
2101 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2102 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2103 if (rdev->pm.i2c_bus) {
2109 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2117 rdev->pm.power_state = kcalloc(num_modes,
2120 if (!rdev->pm.power_state)
2125 if (!rdev->pm.power_state[state_index].clock_info) {
2126 rdev->pm.power_state[state_index].clock_info =
2130 if (!rdev->pm.power_state[state_index].clock_info)
2132 rdev->pm.power_state[state_index].num_clock_modes = 1;
2133 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2136 rdev->pm.power_state[state_index].clock_info[0].mclk =
2138 rdev->pm.power_state[state_index].clock_info[0].sclk =
2141 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2142 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2144 rdev->pm.power_state[state_index].pcie_lanes =
2149 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2151 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2152 radeon_atombios_lookup_gpio(rdev,
2155 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2158 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2161 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2163 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2166 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2167 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2171 rdev->pm.power_state[state_index].clock_info[0].mclk =
2173 rdev->pm.power_state[state_index].clock_info[0].sclk =
2176 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2177 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2179 rdev->pm.power_state[state_index].pcie_lanes =
2185 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2187 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2188 radeon_atombios_lookup_gpio(rdev,
2191 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2194 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2197 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2199 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2202 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2203 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2207 rdev->pm.power_state[state_index].clock_info[0].mclk =
2209 rdev->pm.power_state[state_index].clock_info[0].sclk =
2212 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2213 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2215 rdev->pm.power_state[state_index].pcie_lanes =
2221 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2223 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2224 radeon_atombios_lookup_gpio(rdev,
2227 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2230 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2233 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2235 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2238 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2240 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2244 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2245 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2253 kfree(rdev->pm.power_state[state_index].clock_info);
2254 rdev->pm.power_state[state_index].clock_info = NULL;
2258 if (state_index && rdev->pm.default_power_state_index == -1) {
2259 rdev->pm.power_state[state_index - 1].type =
2261 rdev->pm.default_power_state_index = state_index - 1;
2262 rdev->pm.power_state[state_index - 1].default_clock_mode =
2263 &rdev->pm.power_state[state_index - 1].clock_info[0];
2264 rdev->pm.power_state[state_index - 1].flags &=
2266 rdev->pm.power_state[state_index - 1].misc = 0;
2267 rdev->pm.power_state[state_index - 1].misc2 = 0;
2272 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2280 rdev->pm.no_fan = true;
2281 rdev->pm.fan_pulses_per_revolution =
2283 if (rdev->pm.fan_pulses_per_revolution) {
2284 rdev->pm.fan_min_rpm = controller->ucFanMinRPM;
2285 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM;
2291 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2296 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2301 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2306 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2311 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2316 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2321 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2326 rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2332 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2338 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2344 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2351 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2352 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2353 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2354 if (rdev->pm.i2c_bus) {
2359 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2371 void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2374 struct radeon_mode_info *mode_info = &rdev->mode_info;
2397 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2406 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2408 rdev->pm.power_state[state_index].misc = misc;
2409 rdev->pm.power_state[state_index].misc2 = misc2;
2410 rdev->pm.power_state[state_index].pcie_lanes =
2415 rdev->pm.power_state[state_index].type =
2419 rdev->pm.power_state[state_index].type =
2423 rdev->pm.power_state[state_index].type =
2428 rdev->pm.power_state[state_index].type =
2432 rdev->pm.power_state[state_index].flags = 0;
2434 rdev->pm.power_state[state_index].flags |=
2437 rdev->pm.power_state[state_index].type =
2439 rdev->pm.default_power_state_index = state_index;
2440 rdev->pm.power_state[state_index].default_clock_mode =
2441 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2442 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2444 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2445 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2446 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2447 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2451 if (ASIC_IS_DCE4(rdev))
2452 radeon_atom_get_max_voltage(rdev,
2457 rdev->pm.power_state[state_index].clock_info[j].mclk =
2458 rdev->clock.default_mclk;
2459 rdev->pm.power_state[state_index].clock_info[j].sclk =
2460 rdev->clock.default_sclk;
2462 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2465 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2472 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2479 if (rdev->flags & RADEON_IS_IGP) {
2480 if (rdev->family >= CHIP_PALM) {
2483 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2487 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2489 } else if (rdev->family >= CHIP_BONAIRE) {
2494 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2495 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2496 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2498 } else if (rdev->family >= CHIP_TAHITI) {
2503 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2504 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2505 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2507 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2509 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2511 } else if (rdev->family >= CHIP_CEDAR) {
2516 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2517 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2518 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2520 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2522 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2529 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2530 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2531 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2533 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2538 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2547 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2548 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2550 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2556 if (rdev->flags & RADEON_IS_IGP) {
2558 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2562 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2563 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2569 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2571 struct radeon_mode_info *mode_info = &rdev->mode_info;
2588 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2591 rdev->pm.power_state = kcalloc(power_info->pplib.ucNumStates,
2594 if (!rdev->pm.power_state)
2608 rdev->pm.power_state[i].clock_info =
2613 if (!rdev->pm.power_state[i].clock_info)
2622 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2629 rdev->pm.power_state[state_index].clock_info[0].mclk =
2630 rdev->clock.default_mclk;
2631 rdev->pm.power_state[state_index].clock_info[0].sclk =
2632 rdev->clock.default_sclk;
2635 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2637 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2644 if (rdev->pm.power_state[i].num_clock_modes > 1)
2645 rdev->pm.power_state[i].clock_info[0].flags |=
2649 if (rdev->pm.default_power_state_index == -1) {
2650 rdev->pm.power_state[0].type =
2652 rdev->pm.default_power_state_index = 0;
2653 rdev->pm.power_state[0].default_clock_mode =
2654 &rdev->pm.power_state[0].clock_info[0];
2659 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2661 struct radeon_mode_info *mode_info = &rdev->mode_info;
2682 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2694 rdev->pm.power_state = kcalloc(state_array->ucNumEntries,
2697 if (!rdev->pm.power_state)
2706 rdev->pm.power_state[i].clock_info =
2711 if (!rdev->pm.power_state[i].clock_info)
2718 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2725 rdev->pm.power_state[state_index].clock_info[0].mclk =
2726 rdev->clock.default_mclk;
2727 rdev->pm.power_state[state_index].clock_info[0].sclk =
2728 rdev->clock.default_sclk;
2731 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2733 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2741 if (rdev->pm.power_state[i].num_clock_modes > 1)
2742 rdev->pm.power_state[i].clock_info[0].flags |=
2746 if (rdev->pm.default_power_state_index == -1) {
2747 rdev->pm.power_state[0].type =
2749 rdev->pm.default_power_state_index = 0;
2750 rdev->pm.power_state[0].default_clock_mode =
2751 &rdev->pm.power_state[0].clock_info[0];
2756 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2758 struct radeon_mode_info *mode_info = &rdev->mode_info;
2764 rdev->pm.default_power_state_index = -1;
2772 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2776 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2779 state_index = radeon_atombios_parse_power_table_6(rdev);
2787 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2788 if (rdev->pm.power_state) {
2789 rdev->pm.power_state[0].clock_info =
2793 if (rdev->pm.power_state[0].clock_info) {
2795 rdev->pm.power_state[state_index].type =
2797 rdev->pm.power_state[state_index].num_clock_modes = 1;
2798 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2799 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2800 rdev->pm.power_state[state_index].default_clock_mode =
2801 &rdev->pm.power_state[state_index].clock_info[0];
2802 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2803 rdev->pm.power_state[state_index].pcie_lanes = 16;
2804 rdev->pm.default_power_state_index = state_index;
2805 rdev->pm.power_state[state_index].flags = 0;
2811 rdev->pm.num_power_states = state_index;
2813 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2814 rdev->pm.current_clock_mode_index = 0;
2815 if (rdev->pm.default_power_state_index >= 0)
2816 rdev->pm.current_vddc =
2817 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2819 rdev->pm.current_vddc = 0;
2832 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2845 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2854 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2864 if (rdev->family <= CHIP_RV770) {
2868 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2873 if (rdev->family == CHIP_RV770) {
2883 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2897 if (rdev->family >= CHIP_TAHITI)
2903 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2922 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2933 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2949 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2961 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2974 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3000 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
3007 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3010 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
3015 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3019 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
3024 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3028 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
3036 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3039 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
3045 if (rdev->flags & RADEON_IS_IGP)
3050 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3053 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3069 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3072 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3080 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3083 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3092 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3102 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3108 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3136 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3139 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3146 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3157 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3166 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3178 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3182 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3185 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3192 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3202 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3214 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3229 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3234 (rdev->mode_info.atom_context->bios + data_offset);
3245 (rdev->mode_info.atom_context->bios + data_offset +
3248 (rdev->mode_info.atom_context->bios + data_offset +
3251 (rdev->mode_info.atom_context->bios + data_offset +
3254 (rdev->mode_info.atom_context->bios + data_offset +
3257 (rdev->mode_info.atom_context->bios + data_offset +
3305 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3311 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3315 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3327 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3329 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3336 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3344 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3363 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3439 radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3448 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3451 (rdev->mode_info.atom_context->bios + data_offset);
3497 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3507 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3510 (rdev->mode_info.atom_context->bios + data_offset);
3541 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3550 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3553 (rdev->mode_info.atom_context->bios + data_offset);
3600 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3609 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3612 (rdev->mode_info.atom_context->bios + data_offset);
3650 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3659 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3662 (rdev->mode_info.atom_context->bios + data_offset);
3691 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3698 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3700 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3702 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3717 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3728 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3731 (rdev->mode_info.atom_context->bios + data_offset);
3753 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3818 int radeon_atom_get_memory_info(struct radeon_device *rdev,
3828 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3831 (rdev->mode_info.atom_context->bios + data_offset);
3907 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3920 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3923 (rdev->mode_info.atom_context->bios + data_offset);
3980 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3992 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3995 (rdev->mode_info.atom_context->bios + data_offset);
4073 struct radeon_device *rdev = dev->dev_private;
4076 if (rdev->family >= CHIP_R600) {
4091 if (ASIC_IS_DCE4(rdev))
4094 if (rdev->family >= CHIP_R600) {
4104 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4109 if (rdev->family >= CHIP_R600)
4115 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4118 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4123 if (rdev->family >= CHIP_R600)
4129 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4135 struct radeon_device *rdev = dev->dev_private;
4138 if (rdev->family >= CHIP_R600)
4151 if (rdev->family >= CHIP_R600)
4164 struct radeon_device *rdev = dev->dev_private;
4170 if (rdev->family >= CHIP_R600) {
4333 if (rdev->family >= CHIP_R600) {
4348 struct radeon_device *rdev = dev->dev_private;
4352 if (ASIC_IS_DCE4(rdev))
4355 if (rdev->family >= CHIP_R600)
4393 if (rdev->family >= CHIP_R600)
4403 struct radeon_device *rdev = dev->dev_private;
4407 if (ASIC_IS_DCE4(rdev))
4410 if (rdev->family >= CHIP_R600)
4476 if (rdev->family >= CHIP_R600)