Lines Matching defs:clock
1115 rdev->clock.vco_freq =
1127 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1128 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1129 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1130 struct radeon_pll *spll = &rdev->clock.spll;
1131 struct radeon_pll *mpll = &rdev->clock.mpll;
1181 /* system clock */
1208 /* memory clock */
1235 rdev->clock.default_sclk =
1237 rdev->clock.default_mclk =
1241 rdev->clock.default_dispclk =
1243 if (rdev->clock.default_dispclk == 0) {
1245 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1247 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1249 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1252 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1254 rdev->clock.default_dispclk / 100);
1255 rdev->clock.default_dispclk = 60000;
1257 rdev->clock.dp_extclk =
1259 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1263 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1264 if (rdev->clock.max_pixel_clock == 0)
1265 rdev->clock.max_pixel_clock = 40000;
1267 /* not technically a clock, but... */
1272 rdev->clock.vco_freq =
1275 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1279 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1281 if (rdev->clock.vco_freq == 0)
1282 rdev->clock.vco_freq = 360000; /* 3.6 GHz */
1502 int id, u32 clock)
1536 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1554 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1576 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1635 lvds->native_mode.clock =
1832 mode->crtc_clock = mode->clock =
1876 mode->crtc_clock = mode->clock =
2458 rdev->clock.default_mclk;
2460 rdev->clock.default_sclk;
2630 rdev->clock.default_mclk;
2632 rdev->clock.default_sclk;
2642 /* if multiple clock modes, mark the lowest as no display */
2726 rdev->clock.default_mclk;
2728 rdev->clock.default_sclk;
2739 /* if multiple clock modes, mark the lowest as no display */
2798 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2799 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2834 u32 clock,
2852 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2866 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2881 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2899 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2920 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2931 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2950 u32 clock,
2969 args.ulClock = cpu_to_le32(clock); /* 10 khz */