Lines Matching defs:reg
32 * - surface allocator & initializer : (bit like scratch reg) should
35 * - WB : write back stuff (do it bit like scratch reg things)
668 uint32_t reg[32];
671 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
672 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
1063 unsigned reg;
1071 unsigned idx, unsigned reg);
1854 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1929 int (*set_reg)(struct radeon_device *rdev, int reg,
1932 void (*clear_reg)(struct radeon_device *rdev, int reg);
2456 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2457 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2458 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2462 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2463 return readl(((void __iomem *)rdev->rmmio) + reg);
2465 return r100_mm_rreg_slow(rdev, reg);
2467 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2470 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2471 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2473 r100_mm_wreg_slow(rdev, reg, v);
2476 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2477 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2500 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2501 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2502 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2503 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2504 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2505 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2506 #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \
2507 r100_mm_rreg(rdev, (reg), false))
2508 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2509 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2512 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2513 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2514 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2515 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2516 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2517 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2518 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2519 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2520 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2521 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2522 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2523 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2524 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2525 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2526 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2527 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2528 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2529 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2530 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2531 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2532 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2533 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2534 #define WREG32_P(reg, val, mask) \
2536 uint32_t tmp_ = RREG32(reg); \
2539 WREG32(reg, tmp_); \
2541 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2542 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2543 #define WREG32_PLL_P(reg, val, mask) \
2545 uint32_t tmp_ = RREG32_PLL(reg); \
2548 WREG32_PLL(reg, tmp_); \
2550 #define WREG32_SMC_P(reg, val, mask) \
2552 uint32_t tmp_ = RREG32_SMC(reg); \
2555 WREG32_SMC(reg, tmp_); \
2557 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2558 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2559 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2572 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2573 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2574 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2575 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2576 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2577 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2578 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2579 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2580 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2581 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2582 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2583 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2584 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2585 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2586 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2587 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2955 u32 reg, u32 mask,