Lines Matching defs:offset
178 void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset,
187 WREG32_P(acr_ctl + offset,
193 WREG32_P(HDMI0_ACR_32_0 + offset,
196 WREG32_P(HDMI0_ACR_32_1 + offset,
200 WREG32_P(HDMI0_ACR_44_0 + offset,
203 WREG32_P(HDMI0_ACR_44_1 + offset,
207 WREG32_P(HDMI0_ACR_48_0 + offset,
210 WREG32_P(HDMI0_ACR_48_1 + offset,
218 void r600_set_avi_packet(struct radeon_device *rdev, u32 offset,
223 WREG32(HDMI0_AVI_INFO0 + offset,
225 WREG32(HDMI0_AVI_INFO1 + offset,
227 WREG32(HDMI0_AVI_INFO2 + offset,
229 WREG32(HDMI0_AVI_INFO3 + offset,
232 WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset,
235 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
251 uint32_t offset = dig->afmt->offset;
254 WREG32(HDMI0_AUDIO_INFO0 + offset,
256 WREG32(HDMI0_AUDIO_INFO1 + offset,
269 uint32_t offset = dig->afmt->offset;
271 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
302 uint32_t offset = dig->afmt->offset;
311 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
341 void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset)
346 WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset,
352 void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset)
357 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
367 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
371 WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset,
375 WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset,
384 WREG32_P(HDMI0_60958_0 + offset,
389 WREG32_P(HDMI0_60958_1 + offset,
394 void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
400 WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE);
402 WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE);
421 uint32_t offset;
427 offset = dig->afmt->offset;
449 value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset);
451 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
454 WREG32_OR(HDMI0_CONTROL + offset,
457 WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset,
462 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
519 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
534 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);