Lines Matching defs:rdev
108 static void r600_debugfs_mc_info_init(struct radeon_device *rdev);
111 int r600_mc_wait_for_idle(struct radeon_device *rdev);
112 static void r600_gpu_init(struct radeon_device *rdev);
113 void r600_fini(struct radeon_device *rdev);
114 void r600_irq_disable(struct radeon_device *rdev);
115 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
120 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
125 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
128 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
132 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
136 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
139 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
142 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
147 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
150 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
154 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
158 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
161 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
167 * @rdev: radeon_device pointer
174 int r600_get_allowed_info_register(struct radeon_device *rdev,
193 * @rdev: radeon_device pointer
198 u32 r600_get_xclk(struct radeon_device *rdev)
200 return rdev->clock.spll.reference_freq;
203 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
217 if (rdev->family >= CHIP_RS780)
227 if (rdev->clock.spll.reference_freq == 10000)
232 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
238 if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780)
243 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
251 if (rdev->family >= CHIP_RS780)
279 if (rdev->family >= CHIP_RS780)
282 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
299 struct radeon_device *rdev = dev->dev_private;
350 int rv6xx_get_temp(struct radeon_device *rdev)
362 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
366 rdev->pm.dynpm_can_upclock = true;
367 rdev->pm.dynpm_can_downclock = true;
370 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
373 if (rdev->pm.num_power_states > 2)
376 switch (rdev->pm.dynpm_planned_action) {
378 rdev->pm.requested_power_state_index = min_power_state_index;
379 rdev->pm.requested_clock_mode_index = 0;
380 rdev->pm.dynpm_can_downclock = false;
383 if (rdev->pm.current_power_state_index == min_power_state_index) {
384 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
385 rdev->pm.dynpm_can_downclock = false;
387 if (rdev->pm.active_crtc_count > 1) {
388 for (i = 0; i < rdev->pm.num_power_states; i++) {
389 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
391 else if (i >= rdev->pm.current_power_state_index) {
392 rdev->pm.requested_power_state_index =
393 rdev->pm.current_power_state_index;
396 rdev->pm.requested_power_state_index = i;
401 if (rdev->pm.current_power_state_index == 0)
402 rdev->pm.requested_power_state_index =
403 rdev->pm.num_power_states - 1;
405 rdev->pm.requested_power_state_index =
406 rdev->pm.current_power_state_index - 1;
409 rdev->pm.requested_clock_mode_index = 0;
411 if ((rdev->pm.active_crtc_count > 0) &&
412 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
413 clock_info[rdev->pm.requested_clock_mode_index].flags &
415 rdev->pm.requested_power_state_index++;
419 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
420 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
421 rdev->pm.dynpm_can_upclock = false;
423 if (rdev->pm.active_crtc_count > 1) {
424 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
425 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
427 else if (i <= rdev->pm.current_power_state_index) {
428 rdev->pm.requested_power_state_index =
429 rdev->pm.current_power_state_index;
432 rdev->pm.requested_power_state_index = i;
437 rdev->pm.requested_power_state_index =
438 rdev->pm.current_power_state_index + 1;
440 rdev->pm.requested_clock_mode_index = 0;
443 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
444 rdev->pm.requested_clock_mode_index = 0;
445 rdev->pm.dynpm_can_upclock = false;
456 if (rdev->pm.active_crtc_count > 1) {
457 rdev->pm.requested_power_state_index = -1;
459 for (i = 1; i < rdev->pm.num_power_states; i++) {
460 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
462 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
463 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
464 rdev->pm.requested_power_state_index = i;
469 if (rdev->pm.requested_power_state_index == -1)
470 rdev->pm.requested_power_state_index = 0;
472 rdev->pm.requested_power_state_index = 1;
474 switch (rdev->pm.dynpm_planned_action) {
476 rdev->pm.requested_clock_mode_index = 0;
477 rdev->pm.dynpm_can_downclock = false;
480 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
481 if (rdev->pm.current_clock_mode_index == 0) {
482 rdev->pm.requested_clock_mode_index = 0;
483 rdev->pm.dynpm_can_downclock = false;
485 rdev->pm.requested_clock_mode_index =
486 rdev->pm.current_clock_mode_index - 1;
488 rdev->pm.requested_clock_mode_index = 0;
489 rdev->pm.dynpm_can_downclock = false;
492 if ((rdev->pm.active_crtc_count > 0) &&
493 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
494 clock_info[rdev->pm.requested_clock_mode_index].flags &
496 rdev->pm.requested_clock_mode_index++;
500 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
501 if (rdev->pm.current_clock_mode_index ==
502 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
503 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
504 rdev->pm.dynpm_can_upclock = false;
506 rdev->pm.requested_clock_mode_index =
507 rdev->pm.current_clock_mode_index + 1;
509 rdev->pm.requested_clock_mode_index =
510 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
511 rdev->pm.dynpm_can_upclock = false;
515 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
516 rdev->pm.requested_clock_mode_index = 0;
517 rdev->pm.dynpm_can_upclock = false;
527 rdev->pm.power_state[rdev->pm.requested_power_state_index].
528 clock_info[rdev->pm.requested_clock_mode_index].sclk,
529 rdev->pm.power_state[rdev->pm.requested_power_state_index].
530 clock_info[rdev->pm.requested_clock_mode_index].mclk,
531 rdev->pm.power_state[rdev->pm.requested_power_state_index].
535 void rs780_pm_init_profile(struct radeon_device *rdev)
537 if (rdev->pm.num_power_states == 2) {
539 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
540 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
541 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
542 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
544 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
545 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
546 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
547 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
549 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
550 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
551 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
552 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
554 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
555 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
556 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
557 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
559 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
560 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
561 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
562 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
564 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
565 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
566 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
567 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
569 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
570 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
571 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
572 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
573 } else if (rdev->pm.num_power_states == 3) {
575 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
576 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
577 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
578 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
580 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
581 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
582 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
583 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
585 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
586 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
587 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
588 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
590 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
591 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
592 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
593 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
595 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
596 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
597 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
598 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
600 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
601 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
602 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
603 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
605 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
606 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
607 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
608 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
611 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
612 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
613 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
614 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
616 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
617 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
618 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
619 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
621 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
622 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
623 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
624 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
626 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
627 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
628 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
629 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
631 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
632 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
633 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
634 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
636 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
637 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
638 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
639 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
641 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
642 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
643 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
644 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
648 void r600_pm_init_profile(struct radeon_device *rdev)
652 if (rdev->family == CHIP_R600) {
655 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
656 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
657 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
658 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
660 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
661 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
662 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
663 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
665 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
666 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
667 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
668 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
670 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
671 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
672 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
673 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
675 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
676 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
677 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
678 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
680 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
681 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
682 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
683 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
685 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
686 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
687 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
688 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
690 if (rdev->pm.num_power_states < 4) {
692 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
693 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
694 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
695 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
697 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
698 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
699 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
700 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
702 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
703 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
704 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
705 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
707 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
708 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
709 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
710 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
712 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
713 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
714 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
715 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
717 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
718 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
719 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
720 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
722 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
723 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
724 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
725 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
728 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
729 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
730 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
731 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
733 if (rdev->flags & RADEON_IS_MOBILITY)
734 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
736 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
737 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
738 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
739 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
740 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
742 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
743 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
744 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
745 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
747 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
748 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
749 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
750 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
751 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
753 if (rdev->flags & RADEON_IS_MOBILITY)
754 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
756 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
757 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
758 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
759 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
760 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
762 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
763 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
764 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
765 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
767 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
768 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
769 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
770 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
771 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
776 void r600_pm_misc(struct radeon_device *rdev)
778 int req_ps_idx = rdev->pm.requested_power_state_index;
779 int req_cm_idx = rdev->pm.requested_clock_mode_index;
780 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
787 if (voltage->voltage != rdev->pm.current_vddc) {
788 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
789 rdev->pm.current_vddc = voltage->voltage;
795 bool r600_gui_idle(struct radeon_device *rdev)
804 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
808 if (ASIC_IS_DCE3(rdev)) {
859 void r600_hpd_set_polarity(struct radeon_device *rdev,
863 bool connected = r600_hpd_sense(rdev, hpd);
865 if (ASIC_IS_DCE3(rdev)) {
951 void r600_hpd_init(struct radeon_device *rdev)
953 struct drm_device *dev = rdev->ddev;
968 if (ASIC_IS_DCE3(rdev)) {
970 if (ASIC_IS_DCE32(rdev))
1013 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
1015 radeon_irq_kms_enable_hpd(rdev, enable);
1018 void r600_hpd_fini(struct radeon_device *rdev)
1020 struct drm_device *dev = rdev->ddev;
1026 if (ASIC_IS_DCE3(rdev)) {
1068 radeon_irq_kms_disable_hpd(rdev, disable);
1074 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
1080 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
1081 !(rdev->flags & RADEON_IS_AGP)) {
1082 void __iomem *ptr = (void *)rdev->gart.ptr;
1094 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
1095 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
1097 for (i = 0; i < rdev->usec_timeout; i++) {
1112 int r600_pcie_gart_init(struct radeon_device *rdev)
1116 if (rdev->gart.robj) {
1121 r = radeon_gart_init(rdev);
1124 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
1125 return radeon_gart_table_vram_alloc(rdev);
1128 static int r600_pcie_gart_enable(struct radeon_device *rdev)
1133 if (rdev->gart.robj == NULL) {
1134 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1137 r = radeon_gart_table_vram_pin(rdev);
1168 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1169 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1170 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1174 (u32)(rdev->dummy_page.addr >> 12));
1178 r600_pcie_gart_tlb_flush(rdev);
1180 (unsigned)(rdev->mc.gtt_size >> 20),
1181 (unsigned long long)rdev->gart.table_addr);
1182 rdev->gart.ready = true;
1186 static void r600_pcie_gart_disable(struct radeon_device *rdev)
1218 radeon_gart_table_vram_unpin(rdev);
1221 static void r600_pcie_gart_fini(struct radeon_device *rdev)
1223 radeon_gart_fini(rdev);
1224 r600_pcie_gart_disable(rdev);
1225 radeon_gart_table_vram_free(rdev);
1228 static void r600_agp_enable(struct radeon_device *rdev)
1262 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1267 for (i = 0; i < rdev->usec_timeout; i++) {
1277 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1282 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1286 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1290 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1294 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1299 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1302 static void r600_mc_program(struct radeon_device *rdev)
1318 rv515_mc_stop(rdev, &save);
1319 if (r600_mc_wait_for_idle(rdev)) {
1320 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1325 if (rdev->flags & RADEON_IS_AGP) {
1326 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1329 rdev->mc.vram_start >> 12);
1331 rdev->mc.gtt_end >> 12);
1335 rdev->mc.gtt_start >> 12);
1337 rdev->mc.vram_end >> 12);
1340 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1341 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1343 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1344 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1345 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1347 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1350 if (rdev->flags & RADEON_IS_AGP) {
1351 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1352 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1353 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1359 if (r600_mc_wait_for_idle(rdev)) {
1360 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1362 rv515_mc_resume(rdev, &save);
1365 rv515_vga_render_disable(rdev);
1370 * @rdev: radeon device structure holding all necessary informations
1389 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1395 dev_warn(rdev->dev, "limiting VRAM\n");
1399 if (rdev->flags & RADEON_IS_AGP) {
1404 dev_warn(rdev->dev, "limiting VRAM\n");
1411 dev_warn(rdev->dev, "limiting VRAM\n");
1418 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1423 if (rdev->flags & RADEON_IS_IGP) {
1427 radeon_vram_location(rdev, &rdev->mc, base);
1428 rdev->mc.gtt_base_align = 0;
1429 radeon_gtt_location(rdev, mc);
1433 static int r600_mc_init(struct radeon_device *rdev)
1441 rdev->mc.vram_is_ddr = true;
1466 rdev->mc.vram_width = numchan * chansize;
1468 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1469 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1471 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1472 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1473 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1474 r600_vram_gtt_location(rdev, &rdev->mc);
1476 if (rdev->flags & RADEON_IS_IGP) {
1477 rs690_pm_info(rdev);
1478 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1480 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
1482 rdev->fastfb_working = false;
1487 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1493 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
1495 (unsigned long long)rdev->mc.aper_base, k8_addr);
1496 rdev->mc.aper_base = (resource_size_t)k8_addr;
1497 rdev->fastfb_working = true;
1503 radeon_update_bandwidth_info(rdev);
1507 int r600_vram_scratch_init(struct radeon_device *rdev)
1511 if (rdev->vram_scratch.robj == NULL) {
1512 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1514 0, NULL, NULL, &rdev->vram_scratch.robj);
1520 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1523 r = radeon_bo_pin(rdev->vram_scratch.robj,
1524 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1526 radeon_bo_unreserve(rdev->vram_scratch.robj);
1529 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1530 (void **)&rdev->vram_scratch.ptr);
1532 radeon_bo_unpin(rdev->vram_scratch.robj);
1533 radeon_bo_unreserve(rdev->vram_scratch.robj);
1538 void r600_vram_scratch_fini(struct radeon_device *rdev)
1542 if (rdev->vram_scratch.robj == NULL) {
1545 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1547 radeon_bo_kunmap(rdev->vram_scratch.robj);
1548 radeon_bo_unpin(rdev->vram_scratch.robj);
1549 radeon_bo_unreserve(rdev->vram_scratch.robj);
1551 radeon_bo_unref(&rdev->vram_scratch.robj);
1554 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1566 static void r600_print_gpu_status_regs(struct radeon_device *rdev)
1568 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
1570 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
1572 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
1574 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1576 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1578 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1580 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1582 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1586 static bool r600_is_display_hung(struct radeon_device *rdev)
1592 for (i = 0; i < rdev->num_crtc; i++) {
1600 for (i = 0; i < rdev->num_crtc; i++) {
1615 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
1622 if (rdev->family >= CHIP_RV770) {
1672 if (r600_is_display_hung(rdev))
1684 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1693 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1695 r600_print_gpu_status_regs(rdev);
1698 if (rdev->family >= CHIP_RV770)
1715 rv515_mc_stop(rdev, &save);
1716 if (r600_mc_wait_for_idle(rdev)) {
1717 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1721 if (rdev->family >= CHIP_RV770)
1757 if (rdev->family >= CHIP_RV770)
1775 if (!(rdev->flags & RADEON_IS_IGP)) {
1786 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1800 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1814 rv515_mc_resume(rdev, &save);
1817 r600_print_gpu_status_regs(rdev);
1820 static void r600_gpu_pci_config_reset(struct radeon_device *rdev)
1825 dev_info(rdev->dev, "GPU pci config reset\n");
1830 if (rdev->family >= CHIP_RV770)
1846 if (rdev->family >= CHIP_RV770)
1847 rv770_set_clk_bypass_mode(rdev);
1849 pci_clear_master(rdev->pdev);
1851 rv515_mc_stop(rdev, &save);
1852 if (r600_mc_wait_for_idle(rdev)) {
1853 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1864 radeon_pci_config_reset(rdev);
1874 for (i = 0; i < rdev->usec_timeout; i++) {
1881 int r600_asic_reset(struct radeon_device *rdev, bool hard)
1886 r600_gpu_pci_config_reset(rdev);
1890 reset_mask = r600_gpu_check_soft_reset(rdev);
1893 r600_set_bios_scratch_engine_hung(rdev, true);
1896 r600_gpu_soft_reset(rdev, reset_mask);
1898 reset_mask = r600_gpu_check_soft_reset(rdev);
1902 r600_gpu_pci_config_reset(rdev);
1904 reset_mask = r600_gpu_check_soft_reset(rdev);
1907 r600_set_bios_scratch_engine_hung(rdev, false);
1915 * @rdev: radeon_device pointer
1921 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1923 u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1928 radeon_ring_lockup_update(rdev, ring);
1931 return radeon_ring_test_lockup(rdev, ring);
1934 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1958 if (rdev->family <= CHIP_RV740) {
1989 static void r600_gpu_init(struct radeon_device *rdev)
2004 rdev->config.r600.tiling_group_size = 256;
2005 switch (rdev->family) {
2007 rdev->config.r600.max_pipes = 4;
2008 rdev->config.r600.max_tile_pipes = 8;
2009 rdev->config.r600.max_simds = 4;
2010 rdev->config.r600.max_backends = 4;
2011 rdev->config.r600.max_gprs = 256;
2012 rdev->config.r600.max_threads = 192;
2013 rdev->config.r600.max_stack_entries = 256;
2014 rdev->config.r600.max_hw_contexts = 8;
2015 rdev->config.r600.max_gs_threads = 16;
2016 rdev->config.r600.sx_max_export_size = 128;
2017 rdev->config.r600.sx_max_export_pos_size = 16;
2018 rdev->config.r600.sx_max_export_smx_size = 128;
2019 rdev->config.r600.sq_num_cf_insts = 2;
2023 rdev->config.r600.max_pipes = 2;
2024 rdev->config.r600.max_tile_pipes = 2;
2025 rdev->config.r600.max_simds = 3;
2026 rdev->config.r600.max_backends = 1;
2027 rdev->config.r600.max_gprs = 128;
2028 rdev->config.r600.max_threads = 192;
2029 rdev->config.r600.max_stack_entries = 128;
2030 rdev->config.r600.max_hw_contexts = 8;
2031 rdev->config.r600.max_gs_threads = 4;
2032 rdev->config.r600.sx_max_export_size = 128;
2033 rdev->config.r600.sx_max_export_pos_size = 16;
2034 rdev->config.r600.sx_max_export_smx_size = 128;
2035 rdev->config.r600.sq_num_cf_insts = 2;
2041 rdev->config.r600.max_pipes = 1;
2042 rdev->config.r600.max_tile_pipes = 1;
2043 rdev->config.r600.max_simds = 2;
2044 rdev->config.r600.max_backends = 1;
2045 rdev->config.r600.max_gprs = 128;
2046 rdev->config.r600.max_threads = 192;
2047 rdev->config.r600.max_stack_entries = 128;
2048 rdev->config.r600.max_hw_contexts = 4;
2049 rdev->config.r600.max_gs_threads = 4;
2050 rdev->config.r600.sx_max_export_size = 128;
2051 rdev->config.r600.sx_max_export_pos_size = 16;
2052 rdev->config.r600.sx_max_export_smx_size = 128;
2053 rdev->config.r600.sq_num_cf_insts = 1;
2056 rdev->config.r600.max_pipes = 4;
2057 rdev->config.r600.max_tile_pipes = 4;
2058 rdev->config.r600.max_simds = 4;
2059 rdev->config.r600.max_backends = 4;
2060 rdev->config.r600.max_gprs = 192;
2061 rdev->config.r600.max_threads = 192;
2062 rdev->config.r600.max_stack_entries = 256;
2063 rdev->config.r600.max_hw_contexts = 8;
2064 rdev->config.r600.max_gs_threads = 16;
2065 rdev->config.r600.sx_max_export_size = 128;
2066 rdev->config.r600.sx_max_export_pos_size = 16;
2067 rdev->config.r600.sx_max_export_smx_size = 128;
2068 rdev->config.r600.sq_num_cf_insts = 2;
2088 switch (rdev->config.r600.max_tile_pipes) {
2104 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
2105 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
2120 tmp = rdev->config.r600.max_simds -
2122 rdev->config.r600.active_simds = tmp;
2126 for (i = 0; i < rdev->config.r600.max_backends; i++)
2130 for (i = 0; i < rdev->config.r600.max_backends; i++)
2134 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
2137 rdev->config.r600.backend_map = tmp;
2139 rdev->config.r600.tile_config = tiling_config;
2156 if (rdev->family == CHIP_RV670)
2161 if ((rdev->family > CHIP_R600))
2165 if (((rdev->family) == CHIP_R600) ||
2166 ((rdev->family) == CHIP_RV630) ||
2167 ((rdev->family) == CHIP_RV610) ||
2168 ((rdev->family) == CHIP_RV620) ||
2169 ((rdev->family) == CHIP_RS780) ||
2170 ((rdev->family) == CHIP_RS880)) {
2185 if (((rdev->family) == CHIP_RV610) ||
2186 ((rdev->family) == CHIP_RV620) ||
2187 ((rdev->family) == CHIP_RS780) ||
2188 ((rdev->family) == CHIP_RS880)) {
2193 } else if (((rdev->family) == CHIP_R600) ||
2194 ((rdev->family) == CHIP_RV630)) {
2215 if ((rdev->family) == CHIP_R600) {
2229 } else if (((rdev->family) == CHIP_RV610) ||
2230 ((rdev->family) == CHIP_RV620) ||
2231 ((rdev->family) == CHIP_RS780) ||
2232 ((rdev->family) == CHIP_RS880)) {
2249 } else if (((rdev->family) == CHIP_RV630) ||
2250 ((rdev->family) == CHIP_RV635)) {
2264 } else if ((rdev->family) == CHIP_RV670) {
2287 if (((rdev->family) == CHIP_RV610) ||
2288 ((rdev->family) == CHIP_RV620) ||
2289 ((rdev->family) == CHIP_RS780) ||
2290 ((rdev->family) == CHIP_RS880)) {
2313 tmp = rdev->config.r600.max_pipes * 16;
2314 switch (rdev->family) {
2357 switch (rdev->family) {
2395 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2400 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2404 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2408 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2412 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2417 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2423 void r600_cp_stop(struct radeon_device *rdev)
2425 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2426 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2429 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2432 int r600_init_microcode(struct radeon_device *rdev)
2443 switch (rdev->family) {
2537 if (rdev->family >= CHIP_CEDAR) {
2541 } else if (rdev->family >= CHIP_RV770) {
2554 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
2557 if (rdev->pfp_fw->size != pfp_req_size) {
2559 rdev->pfp_fw->size, fw_name);
2565 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
2568 if (rdev->me_fw->size != me_req_size) {
2570 rdev->me_fw->size, fw_name);
2576 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
2579 if (rdev->rlc_fw->size != rlc_req_size) {
2581 rdev->rlc_fw->size, fw_name);
2586 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) {
2588 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2591 release_firmware(rdev->smc_fw);
2592 rdev->smc_fw = NULL;
2594 } else if (rdev->smc_fw->size != smc_req_size) {
2596 rdev->smc_fw->size, fw_name);
2606 release_firmware(rdev->pfp_fw);
2607 rdev->pfp_fw = NULL;
2608 release_firmware(rdev->me_fw);
2609 rdev->me_fw = NULL;
2610 release_firmware(rdev->rlc_fw);
2611 rdev->rlc_fw = NULL;
2612 release_firmware(rdev->smc_fw);
2613 rdev->smc_fw = NULL;
2618 u32 r600_gfx_get_rptr(struct radeon_device *rdev,
2623 if (rdev->wb.enabled)
2624 rptr = rdev->wb.wb[ring->rptr_offs/4];
2631 u32 r600_gfx_get_wptr(struct radeon_device *rdev,
2637 void r600_gfx_set_wptr(struct radeon_device *rdev,
2644 static int r600_cp_load_microcode(struct radeon_device *rdev)
2649 if (!rdev->me_fw || !rdev->pfp_fw)
2652 r600_cp_stop(rdev);
2668 fw_data = (const __be32 *)rdev->me_fw->data;
2674 fw_data = (const __be32 *)rdev->pfp_fw->data;
2686 int r600_cp_start(struct radeon_device *rdev)
2688 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2692 r = radeon_ring_lock(rdev, ring, 7);
2699 if (rdev->family >= CHIP_RV770) {
2701 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2704 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2709 radeon_ring_unlock_commit(rdev, ring, false);
2716 int r600_cp_resume(struct radeon_device *rdev)
2718 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2749 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2750 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2751 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2753 if (rdev->wb.enabled)
2766 r600_cp_start(rdev);
2768 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2774 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2775 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2780 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2791 if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2792 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2800 void r600_cp_fini(struct radeon_device *rdev)
2802 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2803 r600_cp_stop(rdev);
2804 radeon_ring_fini(rdev, ring);
2805 radeon_scratch_free(rdev, ring->rptr_save_reg);
2811 void r600_scratch_init(struct radeon_device *rdev)
2815 rdev->scratch.num_reg = 7;
2816 rdev->scratch.reg_base = SCRATCH_REG0;
2817 for (i = 0; i < rdev->scratch.num_reg; i++) {
2818 rdev->scratch.free[i] = true;
2819 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2823 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2830 r = radeon_scratch_get(rdev, &scratch);
2836 r = radeon_ring_lock(rdev, ring, 3);
2839 radeon_scratch_free(rdev, scratch);
2845 radeon_ring_unlock_commit(rdev, ring, false);
2846 for (i = 0; i < rdev->usec_timeout; i++) {
2852 if (i < rdev->usec_timeout) {
2859 radeon_scratch_free(rdev, scratch);
2867 void r600_fence_ring_emit(struct radeon_device *rdev,
2870 struct radeon_ring *ring = &rdev->ring[fence->ring];
2874 if (rdev->family >= CHIP_RV770)
2877 if (rdev->wb.use_event) {
2878 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2907 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2918 * @rdev: radeon_device pointer
2926 bool r600_semaphore_ring_emit(struct radeon_device *rdev,
2934 if (rdev->family < CHIP_CAYMAN)
2942 if (emit_wait && (rdev->family >= CHIP_CEDAR)) {
2954 * @rdev: radeon_device pointer
2964 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev,
2971 int ring_index = rdev->asic->copy.blit_ring_index;
2972 struct radeon_ring *ring = &rdev->ring[ring_index];
2981 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24);
2984 radeon_sync_free(rdev, &sync, NULL);
2988 radeon_sync_resv(rdev, &sync, resv, false);
2989 radeon_sync_rings(rdev, &sync, ring->idx);
3015 r = radeon_fence_emit(rdev, &fence, ring->idx);
3017 radeon_ring_unlock_undo(rdev, ring);
3018 radeon_sync_free(rdev, &sync, NULL);
3022 radeon_ring_unlock_commit(rdev, ring, false);
3023 radeon_sync_free(rdev, &sync, fence);
3028 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
3036 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
3041 static void r600_uvd_init(struct radeon_device *rdev)
3045 if (!rdev->has_uvd)
3048 r = radeon_uvd_init(rdev);
3050 dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
3052 * At this point rdev->uvd.vcpu_bo is NULL which trickles down
3057 rdev->has_uvd = false;
3060 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
3061 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
3064 static void r600_uvd_start(struct radeon_device *rdev)
3068 if (!rdev->has_uvd)
3071 r = uvd_v1_0_resume(rdev);
3073 dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
3076 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
3078 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
3084 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
3087 static void r600_uvd_resume(struct radeon_device *rdev)
3092 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
3095 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
3096 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
3098 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
3101 r = uvd_v1_0_init(rdev);
3103 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
3108 static int r600_startup(struct radeon_device *rdev)
3114 r600_pcie_gen2_enable(rdev);
3117 r = r600_vram_scratch_init(rdev);
3121 r600_mc_program(rdev);
3123 if (rdev->flags & RADEON_IS_AGP) {
3124 r600_agp_enable(rdev);
3126 r = r600_pcie_gart_enable(rdev);
3130 r600_gpu_init(rdev);
3133 r = radeon_wb_init(rdev);
3137 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3139 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3143 r600_uvd_start(rdev);
3146 if (!rdev->irq.installed) {
3147 r = radeon_irq_kms_init(rdev);
3152 r = r600_irq_init(rdev);
3155 radeon_irq_kms_fini(rdev);
3158 r600_irq_set(rdev);
3160 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3161 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3166 r = r600_cp_load_microcode(rdev);
3169 r = r600_cp_resume(rdev);
3173 r600_uvd_resume(rdev);
3175 r = radeon_ib_pool_init(rdev);
3177 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3181 r = radeon_audio_init(rdev);
3190 void r600_vga_set_state(struct radeon_device *rdev, bool state)
3204 int r600_resume(struct radeon_device *rdev)
3213 atom_asic_init(rdev->mode_info.atom_context);
3215 if (rdev->pm.pm_method == PM_METHOD_DPM)
3216 radeon_pm_resume(rdev);
3218 rdev->accel_working = true;
3219 r = r600_startup(rdev);
3222 rdev->accel_working = false;
3229 int r600_suspend(struct radeon_device *rdev)
3231 radeon_pm_suspend(rdev);
3232 radeon_audio_fini(rdev);
3233 r600_cp_stop(rdev);
3234 if (rdev->has_uvd) {
3235 radeon_uvd_suspend(rdev);
3236 uvd_v1_0_fini(rdev);
3238 r600_irq_suspend(rdev);
3239 radeon_wb_disable(rdev);
3240 r600_pcie_gart_disable(rdev);
3251 int r600_init(struct radeon_device *rdev)
3255 r600_debugfs_mc_info_init(rdev);
3257 if (!radeon_get_bios(rdev)) {
3258 if (ASIC_IS_AVIVO(rdev))
3262 if (!rdev->is_atom_bios) {
3263 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3266 r = radeon_atombios_init(rdev);
3270 if (!radeon_card_posted(rdev)) {
3271 if (!rdev->bios) {
3272 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3276 atom_asic_init(rdev->mode_info.atom_context);
3279 r600_scratch_init(rdev);
3281 radeon_surface_init(rdev);
3283 radeon_get_clock_info(rdev->ddev);
3285 radeon_fence_driver_init(rdev);
3286 if (rdev->flags & RADEON_IS_AGP) {
3287 r = radeon_agp_init(rdev);
3289 radeon_agp_disable(rdev);
3291 r = r600_mc_init(rdev);
3295 r = radeon_bo_init(rdev);
3299 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3300 r = r600_init_microcode(rdev);
3308 radeon_pm_init(rdev);
3310 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3311 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3313 r600_uvd_init(rdev);
3315 rdev->ih.ring_obj = NULL;
3316 r600_ih_ring_init(rdev, 64 * 1024);
3318 r = r600_pcie_gart_init(rdev);
3322 rdev->accel_working = true;
3323 r = r600_startup(rdev);
3325 dev_err(rdev->dev, "disabling GPU acceleration\n");
3326 r600_cp_fini(rdev);
3327 r600_irq_fini(rdev);
3328 radeon_wb_fini(rdev);
3329 radeon_ib_pool_fini(rdev);
3330 radeon_irq_kms_fini(rdev);
3331 r600_pcie_gart_fini(rdev);
3332 rdev->accel_working = false;
3338 void r600_fini(struct radeon_device *rdev)
3340 radeon_pm_fini(rdev);
3341 radeon_audio_fini(rdev);
3342 r600_cp_fini(rdev);
3343 r600_irq_fini(rdev);
3344 if (rdev->has_uvd) {
3345 uvd_v1_0_fini(rdev);
3346 radeon_uvd_fini(rdev);
3348 radeon_wb_fini(rdev);
3349 radeon_ib_pool_fini(rdev);
3350 radeon_irq_kms_fini(rdev);
3351 r600_pcie_gart_fini(rdev);
3352 r600_vram_scratch_fini(rdev);
3353 radeon_agp_fini(rdev);
3354 radeon_gem_fini(rdev);
3355 radeon_fence_driver_fini(rdev);
3356 radeon_bo_fini(rdev);
3357 radeon_atombios_fini(rdev);
3358 kfree(rdev->bios);
3359 rdev->bios = NULL;
3366 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3368 struct radeon_ring *ring = &rdev->ring[ib->ring];
3377 } else if (rdev->wb.enabled) {
3396 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3404 r = radeon_scratch_get(rdev, &scratch);
3410 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3419 r = radeon_ib_schedule(rdev, &ib, NULL, false);
3435 for (i = 0; i < rdev->usec_timeout; i++) {
3441 if (i < rdev->usec_timeout) {
3449 radeon_ib_free(rdev, &ib);
3451 radeon_scratch_free(rdev, scratch);
3466 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3473 rdev->ih.ring_size = ring_size;
3474 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3475 rdev->ih.rptr = 0;
3478 int r600_ih_ring_alloc(struct radeon_device *rdev)
3483 if (rdev->ih.ring_obj == NULL) {
3484 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3487 NULL, NULL, &rdev->ih.ring_obj);
3492 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3495 r = radeon_bo_pin(rdev->ih.ring_obj,
3497 &rdev->ih.gpu_addr);
3499 radeon_bo_unreserve(rdev->ih.ring_obj);
3503 r = radeon_bo_kmap(rdev->ih.ring_obj,
3504 (void **)&rdev->ih.ring);
3505 radeon_bo_unreserve(rdev->ih.ring_obj);
3514 void r600_ih_ring_fini(struct radeon_device *rdev)
3517 if (rdev->ih.ring_obj) {
3518 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3520 radeon_bo_kunmap(rdev->ih.ring_obj);
3521 radeon_bo_unpin(rdev->ih.ring_obj);
3522 radeon_bo_unreserve(rdev->ih.ring_obj);
3524 radeon_bo_unref(&rdev->ih.ring_obj);
3525 rdev->ih.ring = NULL;
3526 rdev->ih.ring_obj = NULL;
3530 void r600_rlc_stop(struct radeon_device *rdev)
3533 if ((rdev->family >= CHIP_RV770) &&
3534 (rdev->family <= CHIP_RV740)) {
3546 static void r600_rlc_start(struct radeon_device *rdev)
3551 static int r600_rlc_resume(struct radeon_device *rdev)
3556 if (!rdev->rlc_fw)
3559 r600_rlc_stop(rdev);
3571 fw_data = (const __be32 *)rdev->rlc_fw->data;
3572 if (rdev->family >= CHIP_RV770) {
3585 r600_rlc_start(rdev);
3590 static void r600_enable_interrupts(struct radeon_device *rdev)
3599 rdev->ih.enabled = true;
3602 void r600_disable_interrupts(struct radeon_device *rdev)
3614 rdev->ih.enabled = false;
3615 rdev->ih.rptr = 0;
3618 static void r600_disable_interrupt_state(struct radeon_device *rdev)
3629 if (ASIC_IS_DCE3(rdev)) {
3640 if (ASIC_IS_DCE32(rdev)) {
3671 int r600_irq_init(struct radeon_device *rdev)
3678 ret = r600_ih_ring_alloc(rdev);
3683 r600_disable_interrupts(rdev);
3686 if (rdev->family >= CHIP_CEDAR)
3687 ret = evergreen_rlc_resume(rdev);
3689 ret = r600_rlc_resume(rdev);
3691 r600_ih_ring_fini(rdev);
3697 WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8);
3707 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3708 rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
3714 if (rdev->wb.enabled)
3718 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3719 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3730 if (rdev->msi_enabled)
3735 if (rdev->family >= CHIP_CEDAR)
3736 evergreen_disable_interrupt_state(rdev);
3738 r600_disable_interrupt_state(rdev);
3741 pci_set_master(rdev->pdev);
3744 r600_enable_interrupts(rdev);
3749 void r600_irq_suspend(struct radeon_device *rdev)
3751 r600_irq_disable(rdev);
3752 r600_rlc_stop(rdev);
3755 void r600_irq_fini(struct radeon_device *rdev)
3757 r600_irq_suspend(rdev);
3758 r600_ih_ring_fini(rdev);
3761 int r600_irq_set(struct radeon_device *rdev)
3771 if (!rdev->irq.installed) {
3776 if (!rdev->ih.enabled) {
3777 r600_disable_interrupts(rdev);
3779 r600_disable_interrupt_state(rdev);
3783 if (ASIC_IS_DCE3(rdev)) {
3788 if (ASIC_IS_DCE32(rdev)) {
3807 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3810 } else if (rdev->family >= CHIP_RV770) {
3814 if (rdev->irq.dpm_thermal) {
3819 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3825 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3830 if (rdev->irq.crtc_vblank_int[0] ||
3831 atomic_read(&rdev->irq.pflip[0])) {
3835 if (rdev->irq.crtc_vblank_int[1] ||
3836 atomic_read(&rdev->irq.pflip[1])) {
3840 if (rdev->irq.hpd[0]) {
3844 if (rdev->irq.hpd[1]) {
3848 if (rdev->irq.hpd[2]) {
3852 if (rdev->irq.hpd[3]) {
3856 if (rdev->irq.hpd[4]) {
3860 if (rdev->irq.hpd[5]) {
3864 if (rdev->irq.afmt[0]) {
3868 if (rdev->irq.afmt[1]) {
3879 if (ASIC_IS_DCE3(rdev)) {
3884 if (ASIC_IS_DCE32(rdev)) {
3900 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3902 } else if (rdev->family >= CHIP_RV770) {
3912 static void r600_irq_ack(struct radeon_device *rdev)
3916 if (ASIC_IS_DCE3(rdev)) {
3917 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3918 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3919 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3920 if (ASIC_IS_DCE32(rdev)) {
3921 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3922 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3924 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3925 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3928 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3929 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3930 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3931 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3932 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3934 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3935 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3937 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3939 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3941 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3943 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3945 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3947 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3949 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3950 if (ASIC_IS_DCE3(rdev)) {
3960 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3961 if (ASIC_IS_DCE3(rdev)) {
3971 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3972 if (ASIC_IS_DCE3(rdev)) {
3982 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3987 if (ASIC_IS_DCE32(rdev)) {
3988 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3993 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3998 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
4003 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
4009 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
4014 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
4015 if (ASIC_IS_DCE3(rdev)) {
4028 void r600_irq_disable(struct radeon_device *rdev)
4030 r600_disable_interrupts(rdev);
4033 r600_irq_ack(rdev);
4034 r600_disable_interrupt_state(rdev);
4037 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
4041 if (rdev->wb.enabled)
4042 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
4052 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
4053 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
4054 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
4059 return (wptr & rdev->ih.ptr_mask);
4092 int r600_irq_process(struct radeon_device *rdev)
4102 if (!rdev->ih.enabled || rdev->shutdown)
4106 if (!rdev->msi_enabled)
4109 wptr = r600_get_ih_wptr(rdev);
4113 if (atomic_xchg(&rdev->ih.lock, 1))
4116 rptr = rdev->ih.rptr;
4123 r600_irq_ack(rdev);
4128 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
4129 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
4135 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT))
4138 if (rdev->irq.crtc_vblank_int[0]) {
4139 drm_handle_vblank(rdev->ddev, 0);
4140 rdev->pm.vblank_sync = true;
4141 wake_up(&rdev->irq.vblank_queue);
4143 if (atomic_read(&rdev->irq.pflip[0]))
4144 radeon_crtc_handle_vblank(rdev, 0);
4145 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
4150 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT))
4153 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
4165 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT))
4168 if (rdev->irq.crtc_vblank_int[1]) {
4169 drm_handle_vblank(rdev->ddev, 1);
4170 rdev->pm.vblank_sync = true;
4171 wake_up(&rdev->irq.vblank_queue);
4173 if (atomic_read(&rdev->irq.pflip[1]))
4174 radeon_crtc_handle_vblank(rdev, 1);
4175 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
4180 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT))
4183 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
4195 radeon_crtc_handle_flip(rdev, 0);
4200 radeon_crtc_handle_flip(rdev, 1);
4205 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT))
4208 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
4213 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT))
4216 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
4221 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT))
4224 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
4229 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT))
4232 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
4237 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT))
4240 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
4245 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT))
4248 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
4261 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG))
4264 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4270 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG))
4273 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4285 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
4291 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4295 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4299 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4303 rdev->pm.dpm.thermal.high_to_low = false;
4308 rdev->pm.dpm.thermal.high_to_low = true;
4321 rptr &= rdev->ih.ptr_mask;
4325 schedule_delayed_work(&rdev->hotplug_work, 0);
4327 schedule_work(&rdev->audio_work);
4328 if (queue_thermal && rdev->pm.dpm_enabled)
4329 schedule_work(&rdev->pm.dpm.thermal.work);
4330 rdev->ih.rptr = rptr;
4331 atomic_set(&rdev->ih.lock, 0);
4334 wptr = r600_get_ih_wptr(rdev);
4348 struct radeon_device *rdev = m->private;
4350 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4351 DREG32_SYS(m, rdev, VM_L2_STATUS);
4358 static void r600_debugfs_mc_info_init(struct radeon_device *rdev)
4361 struct dentry *root = rdev->ddev->primary->debugfs_root;
4363 debugfs_create_file("r600_mc_info", 0444, root, rdev,
4371 * @rdev: radeon device structure
4378 void r600_mmio_hdp_flush(struct radeon_device *rdev)
4385 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
4386 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
4387 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
4395 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4399 if (rdev->flags & RADEON_IS_IGP)
4402 if (!(rdev->flags & RADEON_IS_PCIE))
4406 if (ASIC_IS_X2(rdev))
4409 radeon_gui_idle(rdev);
4448 int r600_get_pcie_lanes(struct radeon_device *rdev)
4452 if (rdev->flags & RADEON_IS_IGP)
4455 if (!(rdev->flags & RADEON_IS_PCIE))
4459 if (ASIC_IS_X2(rdev))
4462 radeon_gui_idle(rdev);
4485 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4493 if (rdev->flags & RADEON_IS_IGP)
4496 if (!(rdev->flags & RADEON_IS_PCIE))
4500 if (ASIC_IS_X2(rdev))
4504 if (rdev->family <= CHIP_R600)
4507 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
4508 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
4520 if ((rdev->family == CHIP_RV670) ||
4521 (rdev->family == CHIP_RV620) ||
4522 (rdev->family == CHIP_RV635)) {
4545 if ((rdev->family == CHIP_RV670) ||
4546 (rdev->family == CHIP_RV620) ||
4547 (rdev->family == CHIP_RV635)) {
4572 if ((rdev->family == CHIP_RV670) ||
4573 (rdev->family == CHIP_RV620) ||
4574 (rdev->family == CHIP_RV635)) {
4602 * @rdev: radeon_device pointer
4607 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev)
4611 mutex_lock(&rdev->gpu_clock_mutex);
4615 mutex_unlock(&rdev->gpu_clock_mutex);