Lines Matching defs:idx_value
635 u32 idx_value;
639 idx_value = radeon_get_ib_value(p, idx);
671 track->cb[i].offset = idx_value;
673 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
684 track->zb.offset = idx_value;
686 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
714 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */
715 ((idx_value & ~31) + (u32)reloc->gpu_offset);
724 tmp = idx_value + ((u32)reloc->gpu_offset);
734 track->vap_vf_cntl = idx_value;
738 track->vtx_size = idx_value & 0x7F;
742 track->max_indx = idx_value & 0x00FFFFFFUL;
748 track->vap_alt_nverts = idx_value & 0xFFFFFF;
752 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
761 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */
766 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
793 tmp = idx_value & ~(0x7 << 16);
798 track->cb[i].pitch = idx_value & 0x3FFE;
799 switch (((idx_value >> 21) & 0xF)) {
814 ((idx_value >> 21) & 0xF));
829 ((idx_value >> 21) & 0xF));
836 if (idx_value & 2) {
845 switch ((idx_value & 0xF)) {
855 (idx_value & 0xF));
878 tmp = idx_value & ~(0x7 << 16);
882 track->zb.pitch = idx_value & 0x3FFC;
890 enabled = !!(idx_value & (1 << i));
913 tmp = (idx_value >> 25) & 0x3;
915 switch ((idx_value & 0x1F)) {
964 (idx_value & 0x1F));
976 (idx_value & 0x1F));
999 tmp = idx_value & 0x7;
1003 tmp = (idx_value >> 3) & 0x7;
1027 tmp = idx_value & 0x3FFF;
1030 tmp = ((idx_value >> 15) & 1) << 11;
1032 tmp = ((idx_value >> 16) & 1) << 11;
1036 if (idx_value & (1 << 14)) {
1041 } else if (idx_value & (1 << 14)) {
1065 tmp = idx_value & 0x7FF;
1067 tmp = (idx_value >> 11) & 0x7FF;
1069 tmp = (idx_value >> 26) & 0xF;
1071 tmp = idx_value & (1 << 31);
1073 tmp = (idx_value >> 22) & 0xF;
1085 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1089 track->color_channel_mask = idx_value;
1097 if (idx_value & 0x1)
1098 ib[idx] = idx_value & ~1;
1103 track->zb_cb_clear = !!(idx_value & (1 << 5));
1107 if (idx_value & (R300_HIZ_ENABLE |
1116 track->blend_read_enable = !!(idx_value & (1 << 2));
1128 track->aa.offset = idx_value;
1130 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1133 track->aa.pitch = idx_value & 0x3FFE;
1137 track->aaresolve = idx_value & 0x1;
1144 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1148 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1167 reg, idx, idx_value);