Lines Matching defs:temp
1788 uint32_t temp = idx_value >> 4;
1790 track->textures[i].enabled = !!(temp & (1 << i));
2822 uint32_t temp;
2824 temp = RREG32(RADEON_CONFIG_CNTL);
2826 temp &= ~RADEON_CFG_VGA_RAM_EN;
2827 temp |= RADEON_CFG_VGA_IO_DIS;
2829 temp &= ~RADEON_CFG_VGA_IO_DIS;
2831 WREG32(RADEON_CONFIG_CNTL, temp);
3150 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3261 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3262 temp_ff.full = dfixed_const(temp);
3290 temp = RREG32(RADEON_MEM_TIMING_CNTL);
3292 mem_trcd = ((temp >> 2) & 0x3) + 1;
3293 mem_trp = ((temp & 0x3)) + 1;
3294 mem_tras = ((temp & 0x70) >> 4) + 1;
3297 mem_trcd = (temp & 0x7) + 1;
3298 mem_trp = ((temp >> 8) & 0x7) + 1;
3299 mem_tras = ((temp >> 11) & 0xf) + 4;
3303 mem_trcd = (temp & 0x7) + 3;
3304 mem_trp = ((temp >> 8) & 0x7) + 3;
3305 mem_tras = ((temp >> 11) & 0xf) + 6;
3310 mem_trcd = (temp & 0xf) + 3;
3313 mem_trp = ((temp >> 8) & 0xf) + 3;
3316 mem_tras = ((temp >> 12) & 0x1f) + 6;
3320 mem_trcd = (temp & 0x7) + 1;
3321 mem_trp = ((temp >> 8) & 0x7) + 1;
3322 mem_tras = ((temp >> 12) & 0xf) + 4;
3330 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3331 data = (temp & (7 << 20)) >> 20;
3343 data = (temp >> 23) & 0x7;
3351 temp = RREG32(RADEON_MEM_CNTL);
3352 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3354 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3355 temp = RREG32(R300_MC_IND_INDEX);
3356 temp &= ~R300_MC_IND_ADDR_MASK;
3357 temp |= R300_MC_READ_CNTL_CD_mcind;
3358 WREG32(R300_MC_IND_INDEX, temp);
3359 temp = RREG32(R300_MC_IND_DATA);
3360 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3362 temp = RREG32(R300_MC_READ_CNTL_AB);
3363 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3366 temp = RREG32(R300_MC_READ_CNTL_AB);
3367 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3502 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3503 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3504 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3505 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3510 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3511 temp |= RADEON_GRPH_BUFFER_SIZE;
3512 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3518 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3525 temp = RREG32(RS400_DISP1_REG_CNTL);
3526 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3528 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3531 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3532 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3534 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3576 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3577 temp_ff.full = dfixed_const(temp);
3617 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3618 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3620 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3623 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3624 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3626 WREG32(RS400_DISP2_REQ_CNTL2, (temp |