Lines Matching defs:ring
853 * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
855 * @ring: ring buffer struct for emitting packets
857 static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
859 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
860 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
862 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
863 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
871 struct radeon_ring *ring = &rdev->ring[fence->ring];
875 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
876 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
877 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
878 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
880 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
881 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
882 r100_ring_hdp_flush(rdev, ring);
884 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
885 radeon_ring_write(ring, fence->seq);
886 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
887 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
891 struct radeon_ring *ring,
906 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
925 r = radeon_ring_lock(rdev, ring, ndw);
939 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
940 radeon_ring_write(ring,
952 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
953 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
954 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
955 radeon_ring_write(ring, 0);
956 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
957 radeon_ring_write(ring, num_gpu_pages);
958 radeon_ring_write(ring, num_gpu_pages);
959 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
961 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
962 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
963 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
964 radeon_ring_write(ring,
970 radeon_ring_unlock_undo(rdev, ring);
973 radeon_ring_unlock_commit(rdev, ring, false);
992 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
996 r = radeon_ring_lock(rdev, ring, 2);
1000 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
1001 radeon_ring_write(ring,
1006 radeon_ring_unlock_commit(rdev, ring, false);
1073 struct radeon_ring *ring)
1078 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1086 struct radeon_ring *ring)
1092 struct radeon_ring *ring)
1094 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1122 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1142 /* Align ring size */
1146 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1156 ring->align_mask = 16 - 1;
1167 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1185 /* Set ring address */
1186 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1187 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1191 ring->wptr = 0;
1192 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1219 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1220 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1225 ring->ready = true;
1228 if (!ring->rptr_save_reg /* not resuming from suspend */
1229 && radeon_ring_supports_scratch_reg(rdev, ring)) {
1230 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1233 ring->rptr_save_reg = 0;
1244 /* Disable ring */
1246 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1247 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1253 /* Disable ring */
1255 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2526 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2532 radeon_ring_lockup_update(rdev, ring);
2535 return radeon_ring_test_lockup(rdev, ring);
2952 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2956 radeon_ring_free_size(rdev, ring);
2959 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2963 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2964 seq_printf(m, "%u dwords in ring\n", count);
2965 if (ring->ready) {
2967 i = (rdp + j) & ring->ptr_mask;
2968 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
3648 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3661 r = radeon_ring_lock(rdev, ring, 2);
3663 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3667 radeon_ring_write(ring, PACKET0(scratch, 0));
3668 radeon_ring_write(ring, 0xDEADBEEF);
3669 radeon_ring_unlock_commit(rdev, ring, false);
3678 DRM_INFO("ring test succeeded in %d usecs\n", i);
3680 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3690 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3692 if (ring->rptr_save_reg) {
3693 u32 next_rptr = ring->wptr + 2 + 3;
3694 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3695 radeon_ring_write(ring, next_rptr);
3698 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3699 radeon_ring_write(ring, ib->gpu_addr);
3700 radeon_ring_write(ring, ib->length_dw);
3703 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3773 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3917 /* 1M ring buffer */