Lines Matching defs:rdev
77 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
92 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
112 * @rdev: radeon_device pointer
117 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
121 if (crtc >= rdev->num_crtc)
135 while (r100_is_in_vblank(rdev, crtc)) {
137 if (!r100_is_counter_moving(rdev, crtc))
142 while (!r100_is_in_vblank(rdev, crtc)) {
144 if (!r100_is_counter_moving(rdev, crtc))
153 * @rdev: radeon_device pointer
163 void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
165 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
183 for (i = 0; i < rdev->usec_timeout; i++) {
199 * @rdev: radeon_device pointer
205 bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
207 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
217 * @rdev: radeon_device pointer
223 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
226 rdev->pm.dynpm_can_upclock = true;
227 rdev->pm.dynpm_can_downclock = true;
229 switch (rdev->pm.dynpm_planned_action) {
231 rdev->pm.requested_power_state_index = 0;
232 rdev->pm.dynpm_can_downclock = false;
235 if (rdev->pm.current_power_state_index == 0) {
236 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
237 rdev->pm.dynpm_can_downclock = false;
239 if (rdev->pm.active_crtc_count > 1) {
240 for (i = 0; i < rdev->pm.num_power_states; i++) {
241 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
243 else if (i >= rdev->pm.current_power_state_index) {
244 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
247 rdev->pm.requested_power_state_index = i;
252 rdev->pm.requested_power_state_index =
253 rdev->pm.current_power_state_index - 1;
256 if ((rdev->pm.active_crtc_count > 0) &&
257 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
259 rdev->pm.requested_power_state_index++;
263 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
264 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
265 rdev->pm.dynpm_can_upclock = false;
267 if (rdev->pm.active_crtc_count > 1) {
268 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
269 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
271 else if (i <= rdev->pm.current_power_state_index) {
272 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
275 rdev->pm.requested_power_state_index = i;
280 rdev->pm.requested_power_state_index =
281 rdev->pm.current_power_state_index + 1;
285 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
286 rdev->pm.dynpm_can_upclock = false;
294 rdev->pm.requested_clock_mode_index = 0;
297 rdev->pm.power_state[rdev->pm.requested_power_state_index].
298 clock_info[rdev->pm.requested_clock_mode_index].sclk,
299 rdev->pm.power_state[rdev->pm.requested_power_state_index].
300 clock_info[rdev->pm.requested_clock_mode_index].mclk,
301 rdev->pm.power_state[rdev->pm.requested_power_state_index].
308 * @rdev: radeon_device pointer
314 void r100_pm_init_profile(struct radeon_device *rdev)
317 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
318 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
319 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
330 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
332 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
333 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
334 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
337 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
339 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
342 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
343 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
344 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
345 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
347 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
348 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
349 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
350 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
356 * @rdev: radeon_device pointer
361 void r100_pm_misc(struct radeon_device *rdev)
363 int requested_index = rdev->pm.requested_power_state_index;
364 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
441 if ((rdev->flags & RADEON_IS_PCIE) &&
442 !(rdev->flags & RADEON_IS_IGP) &&
443 rdev->asic->pm.set_pcie_lanes &&
445 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
446 radeon_set_pcie_lanes(rdev,
455 * @rdev: radeon_device pointer
459 void r100_pm_prepare(struct radeon_device *rdev)
461 struct drm_device *ddev = rdev->ddev;
486 * @rdev: radeon_device pointer
490 void r100_pm_finish(struct radeon_device *rdev)
492 struct drm_device *ddev = rdev->ddev;
517 * @rdev: radeon_device pointer
522 bool r100_gui_idle(struct radeon_device *rdev)
534 * @rdev: radeon_device pointer
540 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
562 * @rdev: radeon_device pointer
567 void r100_hpd_set_polarity(struct radeon_device *rdev,
571 bool connected = r100_hpd_sense(rdev, hpd);
598 * @rdev: radeon_device pointer
603 void r100_hpd_init(struct radeon_device *rdev)
605 struct drm_device *dev = rdev->ddev;
613 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
615 radeon_irq_kms_enable_hpd(rdev, enable);
621 * @rdev: radeon_device pointer
626 void r100_hpd_fini(struct radeon_device *rdev)
628 struct drm_device *dev = rdev->ddev;
637 radeon_irq_kms_disable_hpd(rdev, disable);
643 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
651 int r100_pci_gart_init(struct radeon_device *rdev)
655 if (rdev->gart.ptr) {
660 r = radeon_gart_init(rdev);
663 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
664 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
665 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
666 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
667 return radeon_gart_table_ram_alloc(rdev);
670 int r100_pci_gart_enable(struct radeon_device *rdev)
678 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
679 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
681 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
684 r100_pci_gart_tlb_flush(rdev);
686 (unsigned)(rdev->mc.gtt_size >> 20),
687 (unsigned long long)rdev->gart.table_addr);
688 rdev->gart.ready = true;
692 void r100_pci_gart_disable(struct radeon_device *rdev)
708 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
711 u32 *gtt = rdev->gart.ptr;
715 void r100_pci_gart_fini(struct radeon_device *rdev)
717 radeon_gart_fini(rdev);
718 r100_pci_gart_disable(rdev);
719 radeon_gart_table_ram_free(rdev);
722 int r100_irq_set(struct radeon_device *rdev)
726 if (!rdev->irq.installed) {
731 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
734 if (rdev->irq.crtc_vblank_int[0] ||
735 atomic_read(&rdev->irq.pflip[0])) {
738 if (rdev->irq.crtc_vblank_int[1] ||
739 atomic_read(&rdev->irq.pflip[1])) {
742 if (rdev->irq.hpd[0]) {
745 if (rdev->irq.hpd[1]) {
756 void r100_irq_disable(struct radeon_device *rdev)
767 static uint32_t r100_irq_ack(struct radeon_device *rdev)
780 int r100_irq_process(struct radeon_device *rdev)
785 status = r100_irq_ack(rdev);
789 if (rdev->shutdown) {
795 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
799 if (rdev->irq.crtc_vblank_int[0]) {
800 drm_handle_vblank(rdev->ddev, 0);
801 rdev->pm.vblank_sync = true;
802 wake_up(&rdev->irq.vblank_queue);
804 if (atomic_read(&rdev->irq.pflip[0]))
805 radeon_crtc_handle_vblank(rdev, 0);
808 if (rdev->irq.crtc_vblank_int[1]) {
809 drm_handle_vblank(rdev->ddev, 1);
810 rdev->pm.vblank_sync = true;
811 wake_up(&rdev->irq.vblank_queue);
813 if (atomic_read(&rdev->irq.pflip[1]))
814 radeon_crtc_handle_vblank(rdev, 1);
824 status = r100_irq_ack(rdev);
827 schedule_delayed_work(&rdev->hotplug_work, 0);
828 if (rdev->msi_enabled) {
829 switch (rdev->family) {
844 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
854 * @rdev: radeon device structure
857 static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
860 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
863 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
868 void r100_fence_ring_emit(struct radeon_device *rdev,
871 struct radeon_ring *ring = &rdev->ring[fence->ring];
882 r100_ring_hdp_flush(rdev, ring);
884 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
890 bool r100_semaphore_ring_emit(struct radeon_device *rdev,
900 struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
906 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
925 r = radeon_ring_lock(rdev, ring, ndw);
968 r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
970 radeon_ring_unlock_undo(rdev, ring);
973 radeon_ring_unlock_commit(rdev, ring, false);
977 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
982 for (i = 0; i < rdev->usec_timeout; i++) {
992 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
996 r = radeon_ring_lock(rdev, ring, 2);
1006 radeon_ring_unlock_commit(rdev, ring, false);
1011 static int r100_cp_init_microcode(struct radeon_device *rdev)
1018 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
1019 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
1020 (rdev->family == CHIP_RS200)) {
1023 } else if ((rdev->family == CHIP_R200) ||
1024 (rdev->family == CHIP_RV250) ||
1025 (rdev->family == CHIP_RV280) ||
1026 (rdev->family == CHIP_RS300)) {
1029 } else if ((rdev->family == CHIP_R300) ||
1030 (rdev->family == CHIP_R350) ||
1031 (rdev->family == CHIP_RV350) ||
1032 (rdev->family == CHIP_RV380) ||
1033 (rdev->family == CHIP_RS400) ||
1034 (rdev->family == CHIP_RS480)) {
1037 } else if ((rdev->family == CHIP_R420) ||
1038 (rdev->family == CHIP_R423) ||
1039 (rdev->family == CHIP_RV410)) {
1042 } else if ((rdev->family == CHIP_RS690) ||
1043 (rdev->family == CHIP_RS740)) {
1046 } else if (rdev->family == CHIP_RS600) {
1049 } else if ((rdev->family == CHIP_RV515) ||
1050 (rdev->family == CHIP_R520) ||
1051 (rdev->family == CHIP_RV530) ||
1052 (rdev->family == CHIP_R580) ||
1053 (rdev->family == CHIP_RV560) ||
1054 (rdev->family == CHIP_RV570)) {
1059 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1062 } else if (rdev->me_fw->size % 8) {
1064 rdev->me_fw->size, fw_name);
1066 release_firmware(rdev->me_fw);
1067 rdev->me_fw = NULL;
1072 u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1077 if (rdev->wb.enabled)
1078 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1085 u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1091 void r100_gfx_set_wptr(struct radeon_device *rdev,
1098 static void r100_cp_load_microcode(struct radeon_device *rdev)
1103 if (r100_gui_wait_for_idle(rdev)) {
1107 if (rdev->me_fw) {
1108 size = rdev->me_fw->size / 4;
1109 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1120 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1122 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1133 r100_debugfs_cp_init(rdev);
1134 if (!rdev->me_fw) {
1135 r = r100_cp_init_microcode(rdev);
1145 r100_cp_load_microcode(rdev);
1146 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1196 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1197 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1199 if (rdev->wb.enabled)
1217 pci_set_master(rdev->pdev);
1219 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1220 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1226 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1229 && radeon_ring_supports_scratch_reg(rdev, ring)) {
1230 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1239 void r100_cp_fini(struct radeon_device *rdev)
1241 if (r100_cp_wait_for_idle(rdev)) {
1245 r100_cp_disable(rdev);
1246 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1247 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1251 void r100_cp_disable(struct radeon_device *rdev)
1254 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1255 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1259 if (r100_gui_wait_for_idle(rdev)) {
1473 crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id);
1968 r = r100_cs_track_check(p->rdev, track);
1980 r = r100_cs_track_check(p->rdev, track);
1992 r = r100_cs_track_check(p->rdev, track);
1999 r = r100_cs_track_check(p->rdev, track);
2006 r = r100_cs_track_check(p->rdev, track);
2013 r = r100_cs_track_check(p->rdev, track);
2020 r = r100_cs_track_check(p->rdev, track);
2027 if (p->rdev->hyperz_filp != p->filp)
2048 r100_cs_track_clear(p->rdev, track);
2058 if (p->rdev->family >= CHIP_R200)
2060 p->rdev->config.r100.reg_safe_bm,
2061 p->rdev->config.r100.reg_safe_bm_size,
2065 p->rdev->config.r100.reg_safe_bm,
2066 p->rdev->config.r100.reg_safe_bm_size,
2132 static int r100_cs_track_cube(struct radeon_device *rdev,
2163 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2184 if (rdev->family < CHIP_R300)
2190 if (rdev->family >= CHIP_RV515)
2197 if (rdev->family >= CHIP_RV515)
2224 ret = r100_cs_track_cube(rdev, track, u);
2245 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2331 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2350 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2377 return r100_cs_track_texture_check(rdev, track);
2382 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2391 if (rdev->family < CHIP_R300) {
2393 if (rdev->family <= CHIP_RS200)
2435 if (rdev->family <= CHIP_RS200) {
2462 static void r100_errata(struct radeon_device *rdev)
2464 rdev->pll_errata = 0;
2466 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2467 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2470 if (rdev->family == CHIP_RV100 ||
2471 rdev->family == CHIP_RS100 ||
2472 rdev->family == CHIP_RS200) {
2473 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2477 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2482 for (i = 0; i < rdev->usec_timeout; i++) {
2492 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2497 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2500 for (i = 0; i < rdev->usec_timeout; i++) {
2510 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2515 for (i = 0; i < rdev->usec_timeout; i++) {
2526 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2532 radeon_ring_lockup_update(rdev, ring);
2535 return radeon_ring_test_lockup(rdev, ring);
2539 void r100_enable_bm(struct radeon_device *rdev)
2547 void r100_bm_disable(struct radeon_device *rdev)
2560 pci_clear_master(rdev->pdev);
2564 int r100_asic_reset(struct radeon_device *rdev, bool hard)
2574 r100_mc_stop(rdev, &save);
2576 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2585 pci_save_state(rdev->pdev);
2587 r100_bm_disable(rdev);
2597 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2605 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2607 pci_restore_state(rdev->pdev);
2608 r100_enable_bm(rdev);
2612 dev_err(rdev->dev, "failed to reset GPU\n");
2615 dev_info(rdev->dev, "GPU reset succeed\n");
2616 r100_mc_resume(rdev, &save);
2620 void r100_set_common_regs(struct radeon_device *rdev)
2639 switch (rdev->pdev->device) {
2649 if ((rdev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2650 ((rdev->pdev->subsystem_device == 0x016c) ||
2651 (rdev->pdev->subsystem_device == 0x016d) ||
2652 (rdev->pdev->subsystem_device == 0x016e) ||
2653 (rdev->pdev->subsystem_device == 0x016f) ||
2654 (rdev->pdev->subsystem_device == 0x0170) ||
2655 (rdev->pdev->subsystem_device == 0x017d) ||
2656 (rdev->pdev->subsystem_device == 0x017e) ||
2657 (rdev->pdev->subsystem_device == 0x0183) ||
2658 (rdev->pdev->subsystem_device == 0x018a) ||
2659 (rdev->pdev->subsystem_device == 0x019a)))
2706 static void r100_vram_get_type(struct radeon_device *rdev)
2710 rdev->mc.vram_is_ddr = false;
2711 if (rdev->flags & RADEON_IS_IGP)
2712 rdev->mc.vram_is_ddr = true;
2714 rdev->mc.vram_is_ddr = true;
2715 if ((rdev->family == CHIP_RV100) ||
2716 (rdev->family == CHIP_RS100) ||
2717 (rdev->family == CHIP_RS200)) {
2720 rdev->mc.vram_width = 32;
2722 rdev->mc.vram_width = 64;
2724 if (rdev->flags & RADEON_SINGLE_CRTC) {
2725 rdev->mc.vram_width /= 4;
2726 rdev->mc.vram_is_ddr = true;
2728 } else if (rdev->family <= CHIP_RV280) {
2731 rdev->mc.vram_width = 128;
2733 rdev->mc.vram_width = 64;
2737 rdev->mc.vram_width = 128;
2741 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2751 if (rdev->family == CHIP_RV280 ||
2752 rdev->family >= CHIP_RV350) {
2763 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2779 void r100_vram_init_sizes(struct radeon_device *rdev)
2784 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2785 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2786 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2788 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2789 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2791 if (rdev->flags & RADEON_IS_IGP) {
2795 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2796 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2797 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2799 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2803 if (rdev->mc.real_vram_size == 0) {
2804 rdev->mc.real_vram_size = 8192 * 1024;
2805 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2810 if (rdev->mc.aper_size > config_aper_size)
2811 config_aper_size = rdev->mc.aper_size;
2813 if (config_aper_size > rdev->mc.real_vram_size)
2814 rdev->mc.mc_vram_size = config_aper_size;
2816 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2820 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2834 static void r100_mc_init(struct radeon_device *rdev)
2838 r100_vram_get_type(rdev);
2839 r100_vram_init_sizes(rdev);
2840 base = rdev->mc.aper_base;
2841 if (rdev->flags & RADEON_IS_IGP)
2843 radeon_vram_location(rdev, &rdev->mc, base);
2844 rdev->mc.gtt_base_align = 0;
2845 if (!(rdev->flags & RADEON_IS_AGP))
2846 radeon_gtt_location(rdev, &rdev->mc);
2847 radeon_update_bandwidth_info(rdev);
2854 void r100_pll_errata_after_index(struct radeon_device *rdev)
2856 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2862 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2867 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2876 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2887 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2892 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2894 r100_pll_errata_after_index(rdev);
2896 r100_pll_errata_after_data(rdev);
2897 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2901 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2905 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2907 r100_pll_errata_after_index(rdev);
2909 r100_pll_errata_after_data(rdev);
2910 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2913 static void r100_set_safe_registers(struct radeon_device *rdev)
2915 if (ASIC_IS_RN50(rdev)) {
2916 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2917 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2918 } else if (rdev->family < CHIP_R200) {
2919 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2920 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2922 r200_set_safe_registers(rdev);
2932 struct radeon_device *rdev = m->private;
2951 struct radeon_device *rdev = m->private;
2952 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2956 radeon_ring_free_size(rdev, ring);
2977 struct radeon_device *rdev = m->private;
3025 struct radeon_device *rdev = m->private;
3058 void r100_debugfs_rbbm_init(struct radeon_device *rdev)
3061 struct dentry *root = rdev->ddev->primary->debugfs_root;
3063 debugfs_create_file("r100_rbbm_info", 0444, root, rdev,
3068 void r100_debugfs_cp_init(struct radeon_device *rdev)
3071 struct dentry *root = rdev->ddev->primary->debugfs_root;
3073 debugfs_create_file("r100_cp_ring_info", 0444, root, rdev,
3075 debugfs_create_file("r100_cp_csq_fifo", 0444, root, rdev,
3080 void r100_debugfs_mc_info_init(struct radeon_device *rdev)
3083 struct dentry *root = rdev->ddev->primary->debugfs_root;
3085 debugfs_create_file("r100_mc_info", 0444, root, rdev,
3090 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3097 if (rdev->family <= CHIP_RS200) {
3107 } else if (rdev->family <= CHIP_RV280) {
3125 if (rdev->family < CHIP_R300)
3138 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3144 void r100_bandwidth_update(struct radeon_device *rdev)
3219 if (!rdev->mode_info.mode_config_initialized)
3222 radeon_update_display_priority(rdev);
3224 if (rdev->mode_info.crtcs[0]->base.enabled) {
3226 rdev->mode_info.crtcs[0]->base.primary->fb;
3228 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3231 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3232 if (rdev->mode_info.crtcs[1]->base.enabled) {
3234 rdev->mode_info.crtcs[1]->base.primary->fb;
3236 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3243 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3258 sclk_ff = rdev->pm.sclk;
3259 mclk_ff = rdev->pm.mclk;
3261 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3291 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3295 } else if (rdev->family == CHIP_R300 ||
3296 rdev->family == CHIP_R350) { /* r300, r350 */
3300 } else if (rdev->family == CHIP_RV350 ||
3301 rdev->family == CHIP_RV380) {
3306 } else if (rdev->family == CHIP_R420 ||
3307 rdev->family == CHIP_R423 ||
3308 rdev->family == CHIP_RV410) {
3332 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3333 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3340 if (rdev->family == CHIP_RS400 ||
3341 rdev->family == CHIP_RS480) {
3348 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3369 if (rdev->family == CHIP_RV410 ||
3370 rdev->family == CHIP_R420 ||
3371 rdev->family == CHIP_R423)
3380 if (rdev->flags & RADEON_IS_AGP) {
3388 if (ASIC_IS_R300(rdev)) {
3391 if ((rdev->family == CHIP_RV100) ||
3392 rdev->flags & RADEON_IS_IGP) {
3393 if (rdev->mc.vram_is_ddr)
3398 if (rdev->mc.vram_width == 128)
3407 if (rdev->mc.vram_is_ddr) {
3408 if (rdev->mc.vram_width == 32) {
3435 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3457 if (ASIC_IS_RV100(rdev))
3486 if (rdev->disp_priority == 2) {
3497 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3506 if ((rdev->family == CHIP_R350) &&
3522 if ((rdev->family == CHIP_RS400) ||
3523 (rdev->family == CHIP_RS480)) {
3562 if ((rdev->family == CHIP_R350) &&
3572 if ((rdev->family == CHIP_RS100) ||
3573 (rdev->family == CHIP_RS200))
3576 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3596 if (rdev->disp_priority == 2) {
3605 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3613 if ((rdev->family == CHIP_RS400) ||
3614 (rdev->family == CHIP_RS480)) {
3642 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
3645 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
3648 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3655 r = radeon_scratch_get(rdev, &scratch);
3661 r = radeon_ring_lock(rdev, ring, 2);
3664 radeon_scratch_free(rdev, scratch);
3669 radeon_ring_unlock_commit(rdev, ring, false);
3670 for (i = 0; i < rdev->usec_timeout; i++) {
3677 if (i < rdev->usec_timeout) {
3684 radeon_scratch_free(rdev, scratch);
3688 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3690 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3703 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3711 r = radeon_scratch_get(rdev, &scratch);
3717 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3731 r = radeon_ib_schedule(rdev, &ib, NULL, false);
3747 for (i = 0; i < rdev->usec_timeout; i++) {
3754 if (i < rdev->usec_timeout) {
3762 radeon_ib_free(rdev, &ib);
3764 radeon_scratch_free(rdev, scratch);
3768 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3773 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3781 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3798 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3810 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3813 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3814 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3815 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3821 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3826 void r100_vga_render_disable(struct radeon_device *rdev)
3834 static void r100_mc_program(struct radeon_device *rdev)
3839 r100_mc_stop(rdev, &save);
3840 if (rdev->flags & RADEON_IS_AGP) {
3842 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3843 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3844 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3845 if (rdev->family > CHIP_RV200)
3847 upper_32_bits(rdev->mc.agp_base) & 0xff);
3851 if (rdev->family > CHIP_RV200)
3855 if (r100_mc_wait_for_idle(rdev))
3856 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3859 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3860 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3861 r100_mc_resume(rdev, &save);
3864 static void r100_clock_startup(struct radeon_device *rdev)
3869 radeon_legacy_set_clock_gating(rdev, 1);
3873 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3878 static int r100_startup(struct radeon_device *rdev)
3883 r100_set_common_regs(rdev);
3885 r100_mc_program(rdev);
3887 r100_clock_startup(rdev);
3890 r100_enable_bm(rdev);
3891 if (rdev->flags & RADEON_IS_PCI) {
3892 r = r100_pci_gart_enable(rdev);
3898 r = radeon_wb_init(rdev);
3902 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3904 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3909 if (!rdev->irq.installed) {
3910 r = radeon_irq_kms_init(rdev);
3915 r100_irq_set(rdev);
3916 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3918 r = r100_cp_init(rdev, 1024 * 1024);
3920 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3924 r = radeon_ib_pool_init(rdev);
3926 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3933 int r100_resume(struct radeon_device *rdev)
3938 if (rdev->flags & RADEON_IS_PCI)
3939 r100_pci_gart_disable(rdev);
3941 r100_clock_startup(rdev);
3943 if (radeon_asic_reset(rdev)) {
3944 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3949 radeon_combios_asic_init(rdev->ddev);
3951 r100_clock_startup(rdev);
3953 radeon_surface_init(rdev);
3955 rdev->accel_working = true;
3956 r = r100_startup(rdev);
3958 rdev->accel_working = false;
3963 int r100_suspend(struct radeon_device *rdev)
3965 radeon_pm_suspend(rdev);
3966 r100_cp_disable(rdev);
3967 radeon_wb_disable(rdev);
3968 r100_irq_disable(rdev);
3969 if (rdev->flags & RADEON_IS_PCI)
3970 r100_pci_gart_disable(rdev);
3974 void r100_fini(struct radeon_device *rdev)
3976 radeon_pm_fini(rdev);
3977 r100_cp_fini(rdev);
3978 radeon_wb_fini(rdev);
3979 radeon_ib_pool_fini(rdev);
3980 radeon_gem_fini(rdev);
3981 if (rdev->flags & RADEON_IS_PCI)
3982 r100_pci_gart_fini(rdev);
3983 radeon_agp_fini(rdev);
3984 radeon_irq_kms_fini(rdev);
3985 radeon_fence_driver_fini(rdev);
3986 radeon_bo_fini(rdev);
3987 radeon_atombios_fini(rdev);
3988 kfree(rdev->bios);
3989 rdev->bios = NULL;
3999 void r100_restore_sanity(struct radeon_device *rdev)
4017 int r100_init(struct radeon_device *rdev)
4022 r100_debugfs_mc_info_init(rdev);
4024 r100_vga_render_disable(rdev);
4026 radeon_scratch_init(rdev);
4028 radeon_surface_init(rdev);
4030 r100_restore_sanity(rdev);
4033 if (!radeon_get_bios(rdev)) {
4034 if (ASIC_IS_AVIVO(rdev))
4037 if (rdev->is_atom_bios) {
4038 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4041 r = radeon_combios_init(rdev);
4046 if (radeon_asic_reset(rdev)) {
4047 dev_warn(rdev->dev,
4053 if (radeon_boot_test_post_card(rdev) == false)
4056 r100_errata(rdev);
4058 radeon_get_clock_info(rdev->ddev);
4060 if (rdev->flags & RADEON_IS_AGP) {
4061 r = radeon_agp_init(rdev);
4063 radeon_agp_disable(rdev);
4067 r100_mc_init(rdev);
4069 radeon_fence_driver_init(rdev);
4071 r = radeon_bo_init(rdev);
4074 if (rdev->flags & RADEON_IS_PCI) {
4075 r = r100_pci_gart_init(rdev);
4079 r100_set_safe_registers(rdev);
4082 radeon_pm_init(rdev);
4084 rdev->accel_working = true;
4085 r = r100_startup(rdev);
4088 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4089 r100_cp_fini(rdev);
4090 radeon_wb_fini(rdev);
4091 radeon_ib_pool_fini(rdev);
4092 radeon_irq_kms_fini(rdev);
4093 if (rdev->flags & RADEON_IS_PCI)
4094 r100_pci_gart_fini(rdev);
4095 rdev->accel_working = false;
4100 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)
4105 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4106 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4107 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4108 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4112 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4116 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4117 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4118 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4119 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4122 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4124 if (reg < rdev->rio_mem_size)
4125 return ioread32(rdev->rio_mem + reg);
4127 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4128 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4132 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4134 if (reg < rdev->rio_mem_size)
4135 iowrite32(v, rdev->rio_mem + reg);
4137 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4138 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);