Lines Matching refs:ret
1009 int ret = 0;
1011 ret = ni_patch_single_dependency_table_based_on_leakage(rdev,
1014 ret = ni_patch_single_dependency_table_based_on_leakage(rdev,
1016 return ret;
1103 int ret;
1105 ret = rv770_read_smc_sram_dword(rdev,
1110 if (ret)
1111 return ret;
1115 ret = rv770_read_smc_sram_dword(rdev,
1120 if (ret)
1121 return ret;
1125 ret = rv770_read_smc_sram_dword(rdev,
1130 if (ret)
1131 return ret;
1135 ret = rv770_read_smc_sram_dword(rdev,
1140 if (ret)
1141 return ret;
1145 ret = rv770_read_smc_sram_dword(rdev,
1150 if (ret)
1151 return ret;
1155 ret = rv770_read_smc_sram_dword(rdev,
1160 if (ret)
1161 return ret;
1165 ret = rv770_read_smc_sram_dword(rdev,
1170 if (ret)
1171 return ret;
1176 return ret;
1388 int ret;
1400 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1403 if (ret)
1406 ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_med);
1407 if (ret)
1410 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1413 if (ret)
1416 ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_high);
1417 if (ret)
1464 int ret;
1471 ret = ni_calculate_adjusted_tdp_limits(rdev,
1476 if (ret)
1477 return ret;
1492 ret = rv770_copy_bytes_to_smc(rdev,
1497 if (ret)
1498 return ret;
1574 int ret;
1576 ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start,
1578 if (ret)
1579 return ret;
1598 int ret;
1600 ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start,
1602 if (ret)
1603 return ret;
1643 int i, ret = 0;
1646 ret = ni_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
1647 if (ret)
1650 ret = rv770_copy_bytes_to_smc(rdev,
1657 if (ret)
1660 return ret;
1688 int ret;
1728 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1731 if (!ret) {
1734 ret = ni_get_std_voltage_value(rdev,
1737 if (!ret)
1807 int ret;
1814 ret = ni_populate_voltage_value(rdev,
1817 if (!ret) {
1820 ret = ni_get_std_voltage_value(rdev,
1822 if (!ret)
1837 ret = ni_populate_voltage_value(rdev,
1841 if (!ret) {
1844 ret = ni_get_std_voltage_value(rdev,
1847 if (!ret)
1942 int ret;
1975 ret = ni_populate_smc_initial_state(rdev, radeon_boot_state, table);
1976 if (ret)
1977 return ret;
1979 ret = ni_populate_smc_acpi_state(rdev, table);
1980 if (ret)
1981 return ret;
1989 ret = ni_do_program_memory_timing_parameters(rdev, radeon_boot_state,
1991 if (ret)
1992 return ret;
2015 int ret;
2017 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2019 if (ret)
2020 return ret;
2074 int ret;
2076 ret = ni_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
2077 if (!ret) {
2087 return ret;
2101 int i, ret;
2112 ret = ni_calculate_sclk_params(rdev, sclk, &sclk_params);
2113 if (ret)
2126 ret = -EINVAL;
2129 ret = -EINVAL;
2132 ret = -EINVAL;
2135 ret = -EINVAL;
2137 if (ret)
2151 if (!ret)
2152 ret = rv770_copy_bytes_to_smc(rdev, ni_pi->spll_table_start, (u8 *)spll_table,
2157 return ret;
2180 int ret;
2183 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
2185 if (ret)
2186 return ret;
2320 int ret;
2328 ret = ni_populate_sclk_value(rdev, pl->sclk, &level->sclk);
2329 if (ret)
2330 return ret;
2360 ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk,
2365 ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk, &level->mclk, 1, 1);
2367 if (ret)
2368 return ret;
2370 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2372 if (ret)
2373 return ret;
2375 ret = ni_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
2376 if (ret)
2377 return ret;
2383 ret = ni_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
2385 if (ret)
2386 return ret;
2391 return ret;
2404 int i, ret;
2419 ret = r600_calculate_at(
2427 ret = r600_calculate_at(
2435 if (ret) {
2465 int i, ret;
2480 ret = ni_calculate_adjusted_tdp_limits(rdev,
2485 if (ret)
2486 return ret;
2490 ret = rv770_write_smc_sram_dword(rdev,
2496 if (ret)
2604 int ret = 0;
2611 ret = -EINVAL;
2620 ret = -EINVAL;
2625 return ret;
2635 int i, ret;
2647 ret = ni_convert_power_level_to_smc(rdev, &state->performance_levels[i],
2652 if (ret)
2653 return ret;
2676 ret = ni_populate_power_containment_values(rdev, radeon_state, smc_state);
2677 if (ret)
2680 ret = ni_populate_sq_ramping_values(rdev, radeon_state, smc_state);
2681 if (ret)
2696 int ret;
2702 ret = ni_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
2703 if (ret)
2706 ret = rv770_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, state_size, pi->sram_end);
2711 return ret;
2877 int ret;
2900 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
2902 if (ret)
2905 ret = ni_copy_vbios_mc_reg_table(table, ni_table);
2907 if (ret)
2912 ret = ni_set_mc_special_registers(rdev, ni_table);
2914 if (ret)
2922 return ret;
3147 int i, ret;
3180 ret = ni_init_driver_calculated_leakage_table(rdev, cac_tables);
3182 ret = ni_init_simplified_leakage_table(rdev, cac_tables);
3184 if (ret)
3197 ret = rv770_copy_bytes_to_smc(rdev, ni_pi->cac_table_start, (u8 *)cac_tables,
3201 if (ret) {
3385 int ret = 0;
3401 ret = -EINVAL;
3418 return ret;
3593 int ret;
3605 ret = cypress_construct_voltage_tables(rdev);
3606 if (ret) {
3608 return ret;
3612 ret = ni_initialize_mc_reg_table(rdev);
3613 if (ret)
3629 ret = rv770_upload_firmware(rdev);
3630 if (ret) {
3632 return ret;
3634 ret = ni_process_firmware_header(rdev);
3635 if (ret) {
3637 return ret;
3639 ret = ni_initial_switch_from_arb_f0_to_f1(rdev);
3640 if (ret) {
3642 return ret;
3644 ret = ni_init_smc_table(rdev);
3645 if (ret) {
3647 return ret;
3649 ret = ni_init_smc_spll_table(rdev);
3650 if (ret) {
3652 return ret;
3654 ret = ni_init_arb_table_index(rdev);
3655 if (ret) {
3657 return ret;
3660 ret = ni_populate_mc_reg_table(rdev, boot_ps);
3661 if (ret) {
3663 return ret;
3666 ret = ni_initialize_smc_cac_tables(rdev);
3667 if (ret) {
3669 return ret;
3671 ret = ni_initialize_hardware_cac_manager(rdev);
3672 if (ret) {
3674 return ret;
3676 ret = ni_populate_smc_tdp_limits(rdev, boot_ps);
3677 if (ret) {
3679 return ret;
3683 ret = cypress_notify_smc_display_change(rdev, false);
3684 if (ret) {
3686 return ret;
3747 int ret;
3749 ret = ni_restrict_performance_levels_before_switch(rdev);
3750 if (ret)
3751 return ret;
3752 ret = rv770_halt_smc(rdev);
3753 if (ret)
3754 return ret;
3755 ret = ni_populate_smc_tdp_limits(rdev, new_ps);
3756 if (ret)
3757 return ret;
3758 ret = rv770_resume_smc(rdev);
3759 if (ret)
3760 return ret;
3761 ret = rv770_set_sw_state(rdev);
3762 if (ret)
3763 return ret;
3786 int ret;
3788 ret = ni_restrict_performance_levels_before_switch(rdev);
3789 if (ret) {
3791 return ret;
3794 ret = ni_enable_power_containment(rdev, new_ps, false);
3795 if (ret) {
3797 return ret;
3799 ret = ni_enable_smc_cac(rdev, new_ps, false);
3800 if (ret) {
3802 return ret;
3804 ret = rv770_halt_smc(rdev);
3805 if (ret) {
3807 return ret;
3811 ret = ni_upload_sw_state(rdev, new_ps);
3812 if (ret) {
3814 return ret;
3817 ret = ni_upload_mc_reg_table(rdev, new_ps);
3818 if (ret) {
3820 return ret;
3823 ret = ni_program_memory_timing_parameters(rdev, new_ps);
3824 if (ret) {
3826 return ret;
3828 ret = rv770_resume_smc(rdev);
3829 if (ret) {
3831 return ret;
3833 ret = rv770_set_sw_state(rdev);
3834 if (ret) {
3836 return ret;
3839 ret = ni_enable_smc_cac(rdev, new_ps, true);
3840 if (ret) {
3842 return ret;
3844 ret = ni_enable_power_containment(rdev, new_ps, true);
3845 if (ret) {
3847 return ret;
3851 ret = ni_power_control_set_level(rdev);
3852 if (ret) {
3854 return ret;
4055 int ret;
4072 ret = r600_get_platform_caps(rdev);
4073 if (ret)
4074 return ret;
4076 ret = ni_parse_power_table(rdev);
4077 if (ret)
4078 return ret;
4079 ret = r600_parse_extended_power_table(rdev);
4080 if (ret)
4081 return ret;
4108 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4110 if (ret)