Lines Matching defs:rdev
724 extern int ni_mc_load_microcode(struct radeon_device *rdev);
726 struct ni_power_info *ni_get_pi(struct radeon_device *rdev)
728 struct ni_power_info *pi = rdev->pm.dpm.priv;
761 static void ni_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
771 bool ni_dpm_vblank_too_short(struct radeon_device *rdev)
773 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
774 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
785 static void ni_apply_state_adjust_rules(struct radeon_device *rdev,
795 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
796 ni_dpm_vblank_too_short(rdev))
801 if (rdev->pm.dpm.ac_power)
802 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
804 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
806 if (rdev->pm.dpm.ac_power == false) {
829 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
864 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
869 btc_adjust_clock_combinations(rdev, max_limits,
873 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
876 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
879 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
882 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
883 rdev->clock.current_dispclk,
888 btc_apply_voltage_delta_rules(rdev,
896 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
899 if (ps->performance_levels[i].vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2)
904 static void ni_cg_clockgating_default(struct radeon_device *rdev)
912 btc_program_mgcg_hw_sequence(rdev, ps, count);
915 static void ni_gfx_clockgating_enable(struct radeon_device *rdev,
929 btc_program_mgcg_hw_sequence(rdev, ps, count);
932 static void ni_mg_clockgating_default(struct radeon_device *rdev)
940 btc_program_mgcg_hw_sequence(rdev, ps, count);
943 static void ni_mg_clockgating_enable(struct radeon_device *rdev,
957 btc_program_mgcg_hw_sequence(rdev, ps, count);
960 static void ni_ls_clockgating_default(struct radeon_device *rdev)
968 btc_program_mgcg_hw_sequence(rdev, ps, count);
971 static void ni_ls_clockgating_enable(struct radeon_device *rdev,
985 btc_program_mgcg_hw_sequence(rdev, ps, count);
989 static int ni_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
992 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1007 static int ni_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
1011 ret = ni_patch_single_dependency_table_based_on_leakage(rdev,
1012 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
1014 ret = ni_patch_single_dependency_table_based_on_leakage(rdev,
1015 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
1019 static void ni_stop_dpm(struct radeon_device *rdev)
1025 static int ni_notify_hw_of_power_source(struct radeon_device *rdev,
1029 return (rv770_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
1036 static PPSMC_Result ni_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1040 return rv770_send_msg_to_smc(rdev, msg);
1043 static int ni_restrict_performance_levels_before_switch(struct radeon_device *rdev)
1045 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
1048 return (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
1052 int ni_dpm_force_performance_level(struct radeon_device *rdev,
1056 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)
1059 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
1062 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
1065 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
1068 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
1071 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)
1075 rdev->pm.dpm.forced_level = level;
1080 static void ni_stop_smc(struct radeon_device *rdev)
1085 for (i = 0; i < rdev->usec_timeout; i++) {
1094 r7xx_stop_smc(rdev);
1097 static int ni_process_firmware_header(struct radeon_device *rdev)
1099 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1100 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1101 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1105 ret = rv770_read_smc_sram_dword(rdev,
1115 ret = rv770_read_smc_sram_dword(rdev,
1125 ret = rv770_read_smc_sram_dword(rdev,
1135 ret = rv770_read_smc_sram_dword(rdev,
1145 ret = rv770_read_smc_sram_dword(rdev,
1155 ret = rv770_read_smc_sram_dword(rdev,
1165 ret = rv770_read_smc_sram_dword(rdev,
1179 static void ni_read_clock_registers(struct radeon_device *rdev)
1181 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1200 static int ni_enter_ulp_state(struct radeon_device *rdev)
1202 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1220 static void ni_program_response_times(struct radeon_device *rdev)
1226 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
1228 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
1229 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
1240 reference_clock = radeon_get_xclk(rdev);
1249 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
1250 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_bbias, bb_dly);
1251 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
1252 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
1253 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
1254 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mclk_switch_lim, mclk_switch_limit);
1257 static void ni_populate_smc_voltage_table(struct radeon_device *rdev,
1269 static void ni_populate_smc_voltage_tables(struct radeon_device *rdev,
1272 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1273 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1277 ni_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
1291 ni_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
1299 static int ni_populate_voltage_value(struct radeon_device *rdev,
1320 static void ni_populate_mvdd_value(struct radeon_device *rdev,
1324 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1325 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1342 static int ni_get_std_voltage_value(struct radeon_device *rdev,
1346 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries &&
1347 ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count))
1348 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
1355 static void ni_populate_std_voltage_value(struct radeon_device *rdev,
1363 static u32 ni_get_smc_power_scaling_factor(struct radeon_device *rdev)
1366 u32 xclk = radeon_get_xclk(rdev);
1380 static u32 ni_calculate_power_boost_limit(struct radeon_device *rdev,
1385 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1386 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1400 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1406 ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_med);
1410 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1416 ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_high);
1432 static int ni_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
1438 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
1442 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
1443 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit + (*tdp_limit - rdev->pm.dpm.tdp_limit);
1445 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
1446 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit - (rdev->pm.dpm.tdp_limit - *tdp_limit);
1452 static int ni_populate_smc_tdp_limits(struct radeon_device *rdev,
1455 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1456 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1460 u32 scaling_factor = ni_get_smc_power_scaling_factor(rdev);
1471 ret = ni_calculate_adjusted_tdp_limits(rdev,
1473 rdev->pm.dpm.tdp_adjustment,
1479 power_boost_limit = ni_calculate_power_boost_limit(rdev, radeon_state,
1492 ret = rv770_copy_bytes_to_smc(rdev,
1504 int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
1569 static int ni_init_arb_table_index(struct radeon_device *rdev)
1571 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1572 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1576 ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start,
1584 return rv770_write_smc_sram_dword(rdev, ni_pi->arb_table_start,
1588 static int ni_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
1590 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
1593 static int ni_force_switch_to_arb_f0(struct radeon_device *rdev)
1595 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1596 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1600 ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start,
1610 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
1613 static int ni_populate_memory_timing_parameters(struct radeon_device *rdev,
1621 (u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk);
1624 radeon_atom_set_engine_dram_timings(rdev, pl->sclk, pl->mclk);
1635 static int ni_do_program_memory_timing_parameters(struct radeon_device *rdev,
1639 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1640 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1646 ret = ni_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
1650 ret = rv770_copy_bytes_to_smc(rdev,
1663 static int ni_program_memory_timing_parameters(struct radeon_device *rdev,
1666 return ni_do_program_memory_timing_parameters(rdev, radeon_new_state,
1670 static void ni_populate_initial_mvdd_value(struct radeon_device *rdev,
1673 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1679 static int ni_populate_smc_initial_state(struct radeon_device *rdev,
1684 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1685 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1686 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1728 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1734 ret = ni_get_std_voltage_value(rdev,
1738 ni_populate_std_voltage_value(rdev, std_vddc,
1744 ni_populate_voltage_value(rdev,
1749 ni_populate_initial_mvdd_value(rdev, &table->initialState.level.mvdd);
1763 cypress_get_strobe_mode_settings(rdev,
1790 static int ni_populate_smc_acpi_state(struct radeon_device *rdev,
1793 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1794 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1795 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1814 ret = ni_populate_voltage_value(rdev,
1820 ret = ni_get_std_voltage_value(rdev,
1823 ni_populate_std_voltage_value(rdev, std_vddc,
1837 ret = ni_populate_voltage_value(rdev,
1844 ret = ni_get_std_voltage_value(rdev,
1848 ni_populate_std_voltage_value(rdev, std_vddc,
1857 ni_populate_voltage_value(rdev,
1919 ni_populate_mvdd_value(rdev, 0, &table->ACPIState.level.mvdd);
1938 static int ni_init_smc_table(struct radeon_device *rdev)
1940 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1941 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1943 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
1948 ni_populate_smc_voltage_tables(rdev, table);
1950 switch (rdev->pm.int_thermal_type) {
1963 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
1966 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1969 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1975 ret = ni_populate_smc_initial_state(rdev, radeon_boot_state, table);
1979 ret = ni_populate_smc_acpi_state(rdev, table);
1989 ret = ni_do_program_memory_timing_parameters(rdev, radeon_boot_state,
1994 return rv770_copy_bytes_to_smc(rdev, pi->state_table_start, (u8 *)table,
1998 static int ni_calculate_sclk_params(struct radeon_device *rdev,
2002 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2003 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2012 u32 reference_clock = rdev->clock.spll.reference_freq;
2017 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2044 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2069 static int ni_populate_sclk_value(struct radeon_device *rdev,
2076 ret = ni_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
2090 static int ni_init_smc_spll_table(struct radeon_device *rdev)
2092 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2093 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2112 ret = ni_calculate_sclk_params(rdev, sclk, &sclk_params);
2152 ret = rv770_copy_bytes_to_smc(rdev, ni_pi->spll_table_start, (u8 *)spll_table,
2160 static int ni_populate_mclk_value(struct radeon_device *rdev,
2167 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2168 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2183 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
2195 ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);
2240 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2242 u32 reference_clock = rdev->clock.mpll.reference_freq;
2298 static void ni_populate_smc_sp(struct radeon_device *rdev,
2303 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2313 static int ni_convert_power_level_to_smc(struct radeon_device *rdev,
2317 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2318 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2319 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2328 ret = ni_populate_sclk_value(rdev, pl->sclk, &level->sclk);
2346 level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk);
2349 if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >=
2360 ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk,
2365 ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk, &level->mclk, 1, 1);
2370 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2375 ret = ni_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
2379 ni_populate_std_voltage_value(rdev, std_vddc,
2383 ret = ni_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
2389 ni_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
2394 static int ni_populate_smc_t(struct radeon_device *rdev,
2398 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2399 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2454 static int ni_populate_power_containment_values(struct radeon_device *rdev,
2458 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2459 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2460 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2480 ret = ni_calculate_adjusted_tdp_limits(rdev,
2482 rdev->pm.dpm.tdp_adjustment,
2488 power_boost_limit = ni_calculate_power_boost_limit(rdev, radeon_state, near_tdp_limit);
2490 ret = rv770_write_smc_sram_dword(rdev,
2494 ni_scale_power_for_smc(power_boost_limit, ni_get_smc_power_scaling_factor(rdev)),
2540 static int ni_populate_sq_ramping_values(struct radeon_device *rdev,
2544 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2557 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2579 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2598 static int ni_enable_power_containment(struct radeon_device *rdev,
2602 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2609 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2618 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2628 static int ni_convert_power_state_to_smc(struct radeon_device *rdev,
2632 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2633 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2647 ret = ni_convert_power_level_to_smc(rdev, &state->performance_levels[i],
2671 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_watermark_threshold,
2674 ni_populate_smc_sp(rdev, radeon_state, smc_state);
2676 ret = ni_populate_power_containment_values(rdev, radeon_state, smc_state);
2680 ret = ni_populate_sq_ramping_values(rdev, radeon_state, smc_state);
2684 return ni_populate_smc_t(rdev, radeon_state, smc_state);
2687 static int ni_upload_sw_state(struct radeon_device *rdev,
2690 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2702 ret = ni_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
2706 ret = rv770_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, state_size, pi->sram_end);
2714 static int ni_set_mc_special_registers(struct radeon_device *rdev,
2717 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2874 static int ni_initialize_mc_reg_table(struct radeon_device *rdev)
2876 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2880 u8 module_index = rv770_get_memory_module_index(rdev);
2900 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
2912 ret = ni_set_mc_special_registers(rdev, ni_table);
2925 static void ni_populate_mc_reg_addresses(struct radeon_device *rdev,
2928 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2960 static void ni_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
2964 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2981 static void ni_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
2989 ni_convert_mc_reg_table_entry_to_smc(rdev,
2995 static int ni_populate_mc_reg_table(struct radeon_device *rdev,
2998 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2999 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3000 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3006 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_seq_index, 1);
3008 ni_populate_mc_reg_addresses(rdev, mc_reg_table);
3010 ni_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
3018 ni_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, mc_reg_table);
3020 return rv770_copy_bytes_to_smc(rdev, eg_pi->mc_reg_table_start,
3026 static int ni_upload_mc_reg_table(struct radeon_device *rdev,
3029 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3030 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3031 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3038 ni_convert_mc_reg_table_to_smc(rdev, radeon_new_state, mc_reg_table);
3043 return rv770_copy_bytes_to_smc(rdev, address,
3049 static int ni_init_driver_calculated_leakage_table(struct radeon_device *rdev,
3052 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3053 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3065 scaling_factor = ni_get_smc_power_scaling_factor(rdev);
3074 ni_calculate_leakage_for_v_and_t(rdev,
3096 static int ni_init_simplified_leakage_table(struct radeon_device *rdev,
3099 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3101 &rdev->pm.dpm.dyn_state.cac_leakage_table;
3121 scaling_factor = ni_get_smc_power_scaling_factor(rdev);
3142 static int ni_initialize_smc_cac_tables(struct radeon_device *rdev)
3144 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3145 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3168 ni_pi->cac_data.i_leakage = rdev->pm.dpm.cac_leakage;
3180 ret = ni_init_driver_calculated_leakage_table(rdev, cac_tables);
3182 ret = ni_init_simplified_leakage_table(rdev, cac_tables);
3197 ret = rv770_copy_bytes_to_smc(rdev, ni_pi->cac_table_start, (u8 *)cac_tables,
3211 static int ni_initialize_hardware_cac_manager(struct radeon_device *rdev)
3213 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3380 static int ni_enable_smc_cac(struct radeon_device *rdev,
3384 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3391 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_CollectCAC_PowerCorreln);
3394 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
3399 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
3406 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
3411 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
3421 static int ni_pcie_performance_request(struct radeon_device *rdev,
3425 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3430 radeon_acpi_pcie_notify_device_ready(rdev);
3432 return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
3436 return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
3442 static int ni_advertise_gen2_capability(struct radeon_device *rdev)
3444 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3456 ni_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, true);
3461 static void ni_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
3464 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3500 static void ni_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
3503 ni_enable_bif_dynamic_pcie_gen2(rdev, enable);
3511 void ni_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
3526 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
3529 void ni_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
3544 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
3547 void ni_dpm_setup_asic(struct radeon_device *rdev)
3549 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3552 r = ni_mc_load_microcode(rdev);
3555 ni_read_clock_registers(rdev);
3556 btc_read_arb_registers(rdev);
3557 rv770_get_memory_type(rdev);
3559 ni_advertise_gen2_capability(rdev);
3560 rv770_get_pcie_gen2_status(rdev);
3561 rv770_enable_acpi_pm(rdev);
3564 void ni_update_current_ps(struct radeon_device *rdev,
3568 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3569 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3576 void ni_update_requested_ps(struct radeon_device *rdev,
3580 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3581 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3588 int ni_dpm_enable(struct radeon_device *rdev)
3590 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3591 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3592 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
3596 ni_cg_clockgating_default(rdev);
3597 if (btc_dpm_enabled(rdev))
3600 ni_mg_clockgating_default(rdev);
3602 ni_ls_clockgating_default(rdev);
3604 rv770_enable_voltage_control(rdev, true);
3605 ret = cypress_construct_voltage_tables(rdev);
3612 ret = ni_initialize_mc_reg_table(rdev);
3617 cypress_enable_spread_spectrum(rdev, true);
3619 rv770_enable_thermal_protection(rdev, true);
3620 rv770_setup_bsp(rdev);
3621 rv770_program_git(rdev);
3622 rv770_program_tp(rdev);
3623 rv770_program_tpp(rdev);
3624 rv770_program_sstp(rdev);
3625 cypress_enable_display_gap(rdev);
3626 rv770_program_vc(rdev);
3628 ni_enable_dynamic_pcie_gen2(rdev, true);
3629 ret = rv770_upload_firmware(rdev);
3634 ret = ni_process_firmware_header(rdev);
3639 ret = ni_initial_switch_from_arb_f0_to_f1(rdev);
3644 ret = ni_init_smc_table(rdev);
3649 ret = ni_init_smc_spll_table(rdev);
3654 ret = ni_init_arb_table_index(rdev);
3660 ret = ni_populate_mc_reg_table(rdev, boot_ps);
3666 ret = ni_initialize_smc_cac_tables(rdev);
3671 ret = ni_initialize_hardware_cac_manager(rdev);
3676 ret = ni_populate_smc_tdp_limits(rdev, boot_ps);
3681 ni_program_response_times(rdev);
3682 r7xx_start_smc(rdev);
3683 ret = cypress_notify_smc_display_change(rdev, false);
3688 cypress_enable_sclk_control(rdev, true);
3690 cypress_enable_mclk_control(rdev, true);
3691 cypress_start_dpm(rdev);
3693 ni_gfx_clockgating_enable(rdev, true);
3695 ni_mg_clockgating_enable(rdev, true);
3697 ni_ls_clockgating_enable(rdev, true);
3699 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
3701 ni_update_current_ps(rdev, boot_ps);
3706 void ni_dpm_disable(struct radeon_device *rdev)
3708 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3709 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3710 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
3712 if (!btc_dpm_enabled(rdev))
3714 rv770_clear_vc(rdev);
3716 rv770_enable_thermal_protection(rdev, false);
3717 ni_enable_power_containment(rdev, boot_ps, false);
3718 ni_enable_smc_cac(rdev, boot_ps, false);
3719 cypress_enable_spread_spectrum(rdev, false);
3720 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
3722 ni_enable_dynamic_pcie_gen2(rdev, false);
3724 if (rdev->irq.installed &&
3725 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
3726 rdev->irq.dpm_thermal = false;
3727 radeon_irq_set(rdev);
3731 ni_gfx_clockgating_enable(rdev, false);
3733 ni_mg_clockgating_enable(rdev, false);
3735 ni_ls_clockgating_enable(rdev, false);
3736 ni_stop_dpm(rdev);
3737 btc_reset_to_default(rdev);
3738 ni_stop_smc(rdev);
3739 ni_force_switch_to_arb_f0(rdev);
3741 ni_update_current_ps(rdev, boot_ps);
3744 static int ni_power_control_set_level(struct radeon_device *rdev)
3746 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
3749 ret = ni_restrict_performance_levels_before_switch(rdev);
3752 ret = rv770_halt_smc(rdev);
3755 ret = ni_populate_smc_tdp_limits(rdev, new_ps);
3758 ret = rv770_resume_smc(rdev);
3761 ret = rv770_set_sw_state(rdev);
3768 int ni_dpm_pre_set_power_state(struct radeon_device *rdev)
3770 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3771 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
3774 ni_update_requested_ps(rdev, new_ps);
3776 ni_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
3781 int ni_dpm_set_power_state(struct radeon_device *rdev)
3783 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3788 ret = ni_restrict_performance_levels_before_switch(rdev);
3793 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
3794 ret = ni_enable_power_containment(rdev, new_ps, false);
3799 ret = ni_enable_smc_cac(rdev, new_ps, false);
3804 ret = rv770_halt_smc(rdev);
3810 btc_notify_uvd_to_smc(rdev, new_ps);
3811 ret = ni_upload_sw_state(rdev, new_ps);
3817 ret = ni_upload_mc_reg_table(rdev, new_ps);
3823 ret = ni_program_memory_timing_parameters(rdev, new_ps);
3828 ret = rv770_resume_smc(rdev);
3833 ret = rv770_set_sw_state(rdev);
3838 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
3839 ret = ni_enable_smc_cac(rdev, new_ps, true);
3844 ret = ni_enable_power_containment(rdev, new_ps, true);
3851 ret = ni_power_control_set_level(rdev);
3860 void ni_dpm_post_set_power_state(struct radeon_device *rdev)
3862 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3865 ni_update_current_ps(rdev, new_ps);
3869 void ni_dpm_reset_asic(struct radeon_device *rdev)
3871 ni_restrict_performance_levels_before_switch(rdev);
3872 rv770_set_boot_state(rdev);
3897 static void ni_parse_pplib_non_clock_info(struct radeon_device *rdev,
3918 rdev->pm.dpm.boot_ps = rps;
3920 rdev->pm.dpm.uvd_ps = rps;
3923 static void ni_parse_pplib_clock_info(struct radeon_device *rdev,
3927 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3928 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3972 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
3973 pl->mclk = rdev->clock.default_mclk;
3974 pl->sclk = rdev->clock.default_sclk;
3981 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
3982 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
3983 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
3984 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
3988 static int ni_parse_power_table(struct radeon_device *rdev)
3990 struct radeon_mode_info *mode_info = &rdev->mode_info;
4006 rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates,
4009 if (!rdev->pm.dpm.ps)
4026 kfree(rdev->pm.dpm.ps);
4029 rdev->pm.dpm.ps[i].ps_priv = ps;
4030 ni_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
4039 ni_parse_pplib_clock_info(rdev,
4040 &rdev->pm.dpm.ps[i], j,
4045 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
4049 int ni_dpm_init(struct radeon_device *rdev)
4060 rdev->pm.dpm.priv = ni_pi;
4064 rv770_get_max_vddc(rdev);
4072 ret = r600_get_platform_caps(rdev);
4076 ret = ni_parse_power_table(rdev);
4079 ret = r600_parse_extended_power_table(rdev);
4083 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
4087 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
4088 r600_free_extended_power_table(rdev);
4091 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
4092 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
4093 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
4094 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
4095 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
4096 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
4097 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
4098 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
4099 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
4101 ni_patch_dependency_tables_based_on_leakage(rdev);
4103 if (rdev->pm.dpm.voltage_response_time == 0)
4104 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
4105 if (rdev->pm.dpm.backbias_response_time == 0)
4106 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
4108 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4132 if (rdev->pdev->device == 0x6707) {
4144 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0);
4147 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0);
4150 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0);
4152 rv770_get_engine_memory_ss(rdev);
4169 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
4187 radeon_acpi_is_pcie_performance_request_supported(rdev);
4200 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 3;
4201 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
4202 rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900;
4203 rdev->pm.dpm.dyn_state.valid_sclk_values.count = ARRAY_SIZE(btc_valid_sclk);
4204 rdev->pm.dpm.dyn_state.valid_sclk_values.values = btc_valid_sclk;
4205 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
4206 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
4207 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 12500;
4214 switch (rdev->pdev->device) {
4264 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
4265 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
4266 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
4267 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4272 void ni_dpm_fini(struct radeon_device *rdev)
4276 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
4277 kfree(rdev->pm.dpm.ps[i].ps_priv);
4279 kfree(rdev->pm.dpm.ps);
4280 kfree(rdev->pm.dpm.priv);
4281 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
4282 r600_free_extended_power_table(rdev);
4285 void ni_dpm_print_power_state(struct radeon_device *rdev,
4297 if (rdev->family >= CHIP_TAHITI)
4304 r600_dpm_print_ps_status(rdev, rps);
4307 void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
4310 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4328 u32 ni_dpm_get_current_sclk(struct radeon_device *rdev)
4330 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4346 u32 ni_dpm_get_current_mclk(struct radeon_device *rdev)
4348 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4364 u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low)
4366 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4375 u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low)
4377 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);