Lines Matching refs:pi
153 struct kv_power_info *pi = rdev->pm.dpm.priv;
155 return pi;
209 struct kv_power_info *pi = kv_get_pi(rdev);
212 if (pi->caps_sq_ramping) {
221 if (pi->caps_db_ramping) {
230 if (pi->caps_td_ramping) {
239 if (pi->caps_tcp_ramping) {
251 struct kv_power_info *pi = kv_get_pi(rdev);
254 if (pi->caps_sq_ramping ||
255 pi->caps_db_ramping ||
256 pi->caps_td_ramping ||
257 pi->caps_tcp_ramping) {
278 struct kv_power_info *pi = kv_get_pi(rdev);
281 if (pi->caps_cac) {
285 pi->cac_enabled = false;
287 pi->cac_enabled = true;
288 } else if (pi->cac_enabled) {
290 pi->cac_enabled = false;
299 struct kv_power_info *pi = kv_get_pi(rdev);
305 &tmp, pi->sram_end);
308 pi->dpm_table_start = tmp;
312 &tmp, pi->sram_end);
315 pi->soft_regs_start = tmp;
322 struct kv_power_info *pi = kv_get_pi(rdev);
325 pi->graphics_voltage_change_enable = 1;
328 pi->dpm_table_start +
330 &pi->graphics_voltage_change_enable,
331 sizeof(u8), pi->sram_end);
338 struct kv_power_info *pi = kv_get_pi(rdev);
341 pi->graphics_interval = 1;
344 pi->dpm_table_start +
346 &pi->graphics_interval,
347 sizeof(u8), pi->sram_end);
354 struct kv_power_info *pi = kv_get_pi(rdev);
358 pi->dpm_table_start +
360 &pi->graphics_boot_level,
361 sizeof(u8), pi->sram_end);
379 struct kv_power_info *pi = kv_get_pi(rdev);
388 pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
389 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);
449 struct kv_power_info *pi = kv_get_pi(rdev);
451 &pi->sys_info.vid_mapping_table,
460 struct kv_power_info *pi = kv_get_pi(rdev);
462 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;
463 pi->graphics_level[index].MinVddNb =
471 struct kv_power_info *pi = kv_get_pi(rdev);
473 pi->graphics_level[index].AT = cpu_to_be16((u16)at);
481 struct kv_power_info *pi = kv_get_pi(rdev);
483 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;
541 struct kv_power_info *pi = kv_get_pi(rdev);
545 if (pi->caps_sclk_throttle_low_notification) {
546 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
549 pi->dpm_table_start +
552 sizeof(u32), pi->sram_end);
559 struct kv_power_info *pi = kv_get_pi(rdev);
565 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
566 if (table->entries[i].clk == pi->boot_pl.sclk)
570 pi->graphics_boot_level = (u8)i;
574 &pi->sys_info.sclk_voltage_mapping_table;
579 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
580 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
584 pi->graphics_boot_level = (u8)i;
592 struct kv_power_info *pi = kv_get_pi(rdev);
595 pi->graphics_therm_throttle_enable = 1;
598 pi->dpm_table_start +
600 &pi->graphics_therm_throttle_enable,
601 sizeof(u8), pi->sram_end);
608 struct kv_power_info *pi = kv_get_pi(rdev);
612 pi->dpm_table_start +
614 (u8 *)&pi->graphics_level,
616 pi->sram_end);
622 pi->dpm_table_start +
624 &pi->graphics_dpm_level_count,
625 sizeof(u8), pi->sram_end);
637 struct kv_power_info *pi = kv_get_pi(rdev);
640 if (pi->caps_enable_dfs_bypass) {
662 struct kv_power_info *pi = kv_get_pi(rdev);
672 pi->uvd_level_count = 0;
674 if (pi->high_voltage_t &&
675 (pi->high_voltage_t < table->entries[i].v))
678 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);
679 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
680 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
682 pi->uvd_level[i].VClkBypassCntl =
684 pi->uvd_level[i].DClkBypassCntl =
691 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
697 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
699 pi->uvd_level_count++;
703 pi->dpm_table_start +
705 (u8 *)&pi->uvd_level_count,
706 sizeof(u8), pi->sram_end);
710 pi->uvd_interval = 1;
713 pi->dpm_table_start +
715 &pi->uvd_interval,
716 sizeof(u8), pi->sram_end);
721 pi->dpm_table_start +
723 (u8 *)&pi->uvd_level,
725 pi->sram_end);
733 struct kv_power_info *pi = kv_get_pi(rdev);
743 pi->vce_level_count = 0;
745 if (pi->high_voltage_t &&
746 pi->high_voltage_t < table->entries[i].v)
749 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);
750 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
752 pi->vce_level[i].ClkBypassCntl =
759 pi->vce_level[i].Divider = (u8)dividers.post_div;
761 pi->vce_level_count++;
765 pi->dpm_table_start +
767 (u8 *)&pi->vce_level_count,
769 pi->sram_end);
773 pi->vce_interval = 1;
776 pi->dpm_table_start +
778 (u8 *)&pi->vce_interval,
780 pi->sram_end);
785 pi->dpm_table_start +
787 (u8 *)&pi->vce_level,
789 pi->sram_end);
796 struct kv_power_info *pi = kv_get_pi(rdev);
806 pi->samu_level_count = 0;
808 if (pi->high_voltage_t &&
809 pi->high_voltage_t < table->entries[i].v)
812 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
813 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
815 pi->samu_level[i].ClkBypassCntl =
822 pi->samu_level[i].Divider = (u8)dividers.post_div;
824 pi->samu_level_count++;
828 pi->dpm_table_start +
830 (u8 *)&pi->samu_level_count,
832 pi->sram_end);
836 pi->samu_interval = 1;
839 pi->dpm_table_start +
841 (u8 *)&pi->samu_interval,
843 pi->sram_end);
848 pi->dpm_table_start +
850 (u8 *)&pi->samu_level,
852 pi->sram_end);
862 struct kv_power_info *pi = kv_get_pi(rdev);
872 pi->acp_level_count = 0;
874 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
875 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
881 pi->acp_level[i].Divider = (u8)dividers.post_div;
883 pi->acp_level_count++;
887 pi->dpm_table_start +
889 (u8 *)&pi->acp_level_count,
891 pi->sram_end);
895 pi->acp_interval = 1;
898 pi->dpm_table_start +
900 (u8 *)&pi->acp_interval,
902 pi->sram_end);
907 pi->dpm_table_start +
909 (u8 *)&pi->acp_level,
911 pi->sram_end);
920 struct kv_power_info *pi = kv_get_pi(rdev);
926 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
927 if (pi->caps_enable_dfs_bypass) {
929 pi->graphics_level[i].ClkBypassCntl = 3;
931 pi->graphics_level[i].ClkBypassCntl = 2;
933 pi->graphics_level[i].ClkBypassCntl = 7;
935 pi->graphics_level[i].ClkBypassCntl = 6;
937 pi->graphics_level[i].ClkBypassCntl = 8;
939 pi->graphics_level[i].ClkBypassCntl = 0;
941 pi->graphics_level[i].ClkBypassCntl = 0;
946 &pi->sys_info.sclk_voltage_mapping_table;
947 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
948 if (pi->caps_enable_dfs_bypass) {
950 pi->graphics_level[i].ClkBypassCntl = 3;
952 pi->graphics_level[i].ClkBypassCntl = 2;
954 pi->graphics_level[i].ClkBypassCntl = 7;
956 pi->graphics_level[i].ClkBypassCntl = 6;
958 pi->graphics_level[i].ClkBypassCntl = 8;
960 pi->graphics_level[i].ClkBypassCntl = 0;
962 pi->graphics_level[i].ClkBypassCntl = 0;
976 struct kv_power_info *pi = kv_get_pi(rdev);
978 pi->acp_boot_level = 0xff;
985 struct kv_power_info *pi = kv_get_pi(rdev);
987 pi->current_rps = *rps;
988 pi->current_ps = *new_ps;
989 pi->current_rps.ps_priv = &pi->current_ps;
996 struct kv_power_info *pi = kv_get_pi(rdev);
998 pi->requested_rps = *rps;
999 pi->requested_ps = *new_ps;
1000 pi->requested_rps.ps_priv = &pi->requested_ps;
1005 struct kv_power_info *pi = kv_get_pi(rdev);
1008 if (pi->bapm_enable) {
1030 struct kv_power_info *pi = kv_get_pi(rdev);
1074 if (pi->enable_auto_thermal_throttling) {
1175 struct kv_power_info *pi = kv_get_pi(rdev);
1177 pi->low_sclk_interrupt_t = 0;
1182 struct kv_power_info *pi = kv_get_pi(rdev);
1185 if (pi->caps_fps) {
1189 pi->fps_high_t = cpu_to_be16(tmp);
1191 pi->dpm_table_start +
1193 (u8 *)&pi->fps_high_t,
1194 sizeof(u16), pi->sram_end);
1197 pi->fps_low_t = cpu_to_be16(tmp);
1200 pi->dpm_table_start +
1202 (u8 *)&pi->fps_low_t,
1203 sizeof(u16), pi->sram_end);
1211 struct kv_power_info *pi = kv_get_pi(rdev);
1213 pi->uvd_power_gated = false;
1214 pi->vce_power_gated = false;
1215 pi->samu_power_gated = false;
1216 pi->acp_power_gated = false;
1246 struct kv_power_info *pi = kv_get_pi(rdev);
1254 pi->uvd_boot_level = table->count - 1;
1256 pi->uvd_boot_level = 0;
1258 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) {
1259 mask = 1 << pi->uvd_boot_level;
1265 pi->dpm_table_start +
1267 (uint8_t *)&pi->uvd_boot_level,
1268 sizeof(u8), pi->sram_end);
1298 struct kv_power_info *pi = kv_get_pi(rdev);
1307 if (pi->caps_stable_p_state)
1308 pi->vce_boot_level = table->count - 1;
1310 pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk);
1313 pi->dpm_table_start +
1315 (u8 *)&pi->vce_boot_level,
1317 pi->sram_end);
1321 if (pi->caps_stable_p_state)
1324 (1 << pi->vce_boot_level));
1339 struct kv_power_info *pi = kv_get_pi(rdev);
1345 if (pi->caps_stable_p_state)
1346 pi->samu_boot_level = table->count - 1;
1348 pi->samu_boot_level = 0;
1351 pi->dpm_table_start +
1353 (u8 *)&pi->samu_boot_level,
1355 pi->sram_end);
1359 if (pi->caps_stable_p_state)
1362 (1 << pi->samu_boot_level));
1387 struct kv_power_info *pi = kv_get_pi(rdev);
1390 if (!pi->caps_stable_p_state) {
1392 if (acp_boot_level != pi->acp_boot_level) {
1393 pi->acp_boot_level = acp_boot_level;
1396 (1 << pi->acp_boot_level));
1403 struct kv_power_info *pi = kv_get_pi(rdev);
1409 if (pi->caps_stable_p_state)
1410 pi->acp_boot_level = table->count - 1;
1412 pi->acp_boot_level = kv_get_acp_boot_level(rdev);
1415 pi->dpm_table_start +
1417 (u8 *)&pi->acp_boot_level,
1419 pi->sram_end);
1423 if (pi->caps_stable_p_state)
1426 (1 << pi->acp_boot_level));
1434 struct kv_power_info *pi = kv_get_pi(rdev);
1436 if (pi->uvd_power_gated == gate)
1439 pi->uvd_power_gated = gate;
1442 if (pi->caps_uvd_pg) {
1447 if (pi->caps_uvd_pg)
1450 if (pi->caps_uvd_pg) {
1462 struct kv_power_info *pi = kv_get_pi(rdev);
1464 if (pi->vce_power_gated == gate)
1467 pi->vce_power_gated = gate;
1470 if (pi->caps_vce_pg) {
1475 if (pi->caps_vce_pg) {
1485 struct kv_power_info *pi = kv_get_pi(rdev);
1487 if (pi->samu_power_gated == gate)
1490 pi->samu_power_gated = gate;
1494 if (pi->caps_samu_pg)
1497 if (pi->caps_samu_pg)
1505 struct kv_power_info *pi = kv_get_pi(rdev);
1507 if (pi->acp_power_gated == gate)
1513 pi->acp_power_gated = gate;
1517 if (pi->caps_acp_pg)
1520 if (pi->caps_acp_pg)
1530 struct kv_power_info *pi = kv_get_pi(rdev);
1536 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1538 (i == (pi->graphics_dpm_level_count - 1))) {
1539 pi->lowest_valid = i;
1544 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1548 pi->highest_valid = i;
1550 if (pi->lowest_valid > pi->highest_valid) {
1551 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
1552 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
1553 pi->highest_valid = pi->lowest_valid;
1555 pi->lowest_valid = pi->highest_valid;
1559 &pi->sys_info.sclk_voltage_mapping_table;
1561 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) {
1563 i == (int)(pi->graphics_dpm_level_count - 1)) {
1564 pi->lowest_valid = i;
1569 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1574 pi->highest_valid = i;
1576 if (pi->lowest_valid > pi->highest_valid) {
1578 table->entries[pi->highest_valid].sclk_frequency) >
1579 (table->entries[pi->lowest_valid].sclk_frequency -
1581 pi->highest_valid = pi->lowest_valid;
1583 pi->lowest_valid = pi->highest_valid;
1592 struct kv_power_info *pi = kv_get_pi(rdev);
1596 if (pi->caps_enable_dfs_bypass) {
1598 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0;
1600 (pi->dpm_table_start +
1602 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) +
1605 sizeof(u8), pi->sram_end);
1614 struct kv_power_info *pi = kv_get_pi(rdev);
1618 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
1621 pi->nb_dpm_enabled = true;
1624 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) {
1627 pi->nb_dpm_enabled = false;
1660 struct kv_power_info *pi = kv_get_pi(rdev);
1667 &pi->requested_rps,
1668 &pi->current_rps);
1675 struct kv_power_info *pi = kv_get_pi(rdev);
1676 struct radeon_ps *new_ps = &pi->requested_rps;
1677 struct radeon_ps *old_ps = &pi->current_rps;
1680 if (pi->bapm_enable) {
1689 if (pi->enable_dpm) {
1718 if (pi->enable_dpm) {
1749 struct kv_power_info *pi = kv_get_pi(rdev);
1750 struct radeon_ps *new_ps = &pi->requested_rps;
1767 struct kv_power_info *pi = kv_get_pi(rdev);
1769 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) {
1770 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1;
1772 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency;
1775 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit);
1778 table->mclk = pi->sys_info.nbp_memory_clock[0];
1825 struct kv_power_info *pi = kv_get_pi(rdev);
1827 pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
1828 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
1829 pi->boot_pl.ds_divider_index = 0;
1830 pi->boot_pl.ss_divider_index = 0;
1831 pi->boot_pl.allow_gnb_slow = 1;
1832 pi->boot_pl.force_nbp_state = 0;
1833 pi->boot_pl.display_wm = 0;
1834 pi->boot_pl.vce_wm = 0;
1880 struct kv_power_info *pi = kv_get_pi(rdev);
1889 if (!pi->caps_sclk_ds)
1903 struct kv_power_info *pi = kv_get_pi(rdev);
1910 if (pi->high_voltage_t &&
1912 pi->high_voltage_t)) {
1919 &pi->sys_info.sclk_voltage_mapping_table;
1922 if (pi->high_voltage_t &&
1924 pi->high_voltage_t)) {
1940 struct kv_power_info *pi = kv_get_pi(rdev);
1962 if (pi->caps_stable_p_state) {
1992 if (pi->high_voltage_t &&
1993 (pi->high_voltage_t <
2001 &pi->sys_info.sclk_voltage_mapping_table;
2004 if (pi->high_voltage_t &&
2005 (pi->high_voltage_t <
2013 if (pi->caps_stable_p_state) {
2019 pi->video_start = new_rps->dclk || new_rps->vclk ||
2024 pi->battery_state = true;
2026 pi->battery_state = false;
2039 if (pi->sys_info.nb_dpm_enable) {
2040 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2041 pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) ||
2042 pi->disable_nb_ps3_in_battery;
2054 struct kv_power_info *pi = kv_get_pi(rdev);
2056 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;
2061 struct kv_power_info *pi = kv_get_pi(rdev);
2065 if (pi->lowest_valid > pi->highest_valid)
2068 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2069 pi->graphics_level[i].DeepSleepDivId =
2071 be32_to_cpu(pi->graphics_level[i].SclkFrequency),
2079 struct kv_power_info *pi = kv_get_pi(rdev);
2086 if (pi->lowest_valid > pi->highest_valid)
2090 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2091 pi->graphics_level[i].GnbSlow = 1;
2092 pi->graphics_level[i].ForceNbPs1 = 0;
2093 pi->graphics_level[i].UpH = 0;
2096 if (!pi->sys_info.nb_dpm_enable)
2099 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2100 (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);
2103 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2104 pi->graphics_level[i].GnbSlow = 0;
2106 if (pi->battery_state)
2107 pi->graphics_level[0].ForceNbPs1 = 1;
2109 pi->graphics_level[1].GnbSlow = 0;
2110 pi->graphics_level[2].GnbSlow = 0;
2111 pi->graphics_level[3].GnbSlow = 0;
2112 pi->graphics_level[4].GnbSlow = 0;
2115 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2116 pi->graphics_level[i].GnbSlow = 1;
2117 pi->graphics_level[i].ForceNbPs1 = 0;
2118 pi->graphics_level[i].UpH = 0;
2121 if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
2122 pi->graphics_level[pi->lowest_valid].UpH = 0x28;
2123 pi->graphics_level[pi->lowest_valid].GnbSlow = 0;
2124 if (pi->lowest_valid != pi->highest_valid)
2125 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1;
2133 struct kv_power_info *pi = kv_get_pi(rdev);
2136 if (pi->lowest_valid > pi->highest_valid)
2139 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2140 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0;
2147 struct kv_power_info *pi = kv_get_pi(rdev);
2155 pi->graphics_dpm_level_count = 0;
2157 if (pi->high_voltage_t &&
2158 (pi->high_voltage_t <
2164 &pi->sys_info.vid_mapping_table,
2167 kv_set_at(rdev, i, pi->at[i]);
2169 pi->graphics_dpm_level_count++;
2173 &pi->sys_info.sclk_voltage_mapping_table;
2175 pi->graphics_dpm_level_count = 0;
2177 if (pi->high_voltage_t &&
2178 pi->high_voltage_t <
2184 kv_set_at(rdev, i, pi->at[i]);
2186 pi->graphics_dpm_level_count++;
2196 struct kv_power_info *pi = kv_get_pi(rdev);
2200 if (i >= pi->lowest_valid && i <= pi->highest_valid)
2216 struct kv_power_info *pi = kv_get_pi(rdev);
2219 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2231 struct kv_power_info *pi = kv_get_pi(rdev);
2237 if (pi->sys_info.nb_dpm_enable) {
2288 struct kv_power_info *pi = kv_get_pi(rdev);
2305 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock);
2306 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock);
2307 pi->sys_info.bootup_nb_voltage_index =
2310 pi->sys_info.htc_tmp_lmt = 203;
2312 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt;
2314 pi->sys_info.htc_hyst_lmt = 5;
2316 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt;
2317 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
2322 pi->sys_info.nb_dpm_enable = true;
2324 pi->sys_info.nb_dpm_enable = false;
2327 pi->sys_info.nbp_memory_clock[i] =
2329 pi->sys_info.nbp_n_clock[i] =
2334 pi->caps_enable_dfs_bypass = true;
2337 &pi->sys_info.sclk_voltage_mapping_table,
2341 &pi->sys_info.vid_mapping_table,
2374 struct kv_power_info *pi = kv_get_pi(rdev);
2377 ps->levels[0] = pi->boot_pl;
2411 struct kv_power_info *pi = kv_get_pi(rdev);
2423 if (pi->caps_sclk_ds) {
2521 struct kv_power_info *pi;
2524 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL);
2525 if (pi == NULL)
2527 rdev->pm.dpm.priv = pi;
2538 pi->at[i] = TRINITY_AT_DFLT;
2540 pi->sram_end = SMC_RAM_END;
2544 pi->enable_nb_dpm = false;
2546 pi->enable_nb_dpm = true;
2548 pi->caps_power_containment = true;
2549 pi->caps_cac = true;
2550 pi->enable_didt = false;
2551 if (pi->enable_didt) {
2552 pi->caps_sq_ramping = true;
2553 pi->caps_db_ramping = true;
2554 pi->caps_td_ramping = true;
2555 pi->caps_tcp_ramping = true;
2558 pi->caps_sclk_ds = true;
2559 pi->enable_auto_thermal_throttling = true;
2560 pi->disable_nb_ps3_in_battery = false;
2564 pi->bapm_enable = true;
2566 pi->bapm_enable = false;
2568 pi->bapm_enable = false;
2570 pi->bapm_enable = true;
2572 pi->voltage_drop_t = 0;
2573 pi->caps_sclk_throttle_low_notification = false;
2574 pi->caps_fps = false; /* true? */
2575 pi->caps_uvd_pg = true;
2576 pi->caps_uvd_dpm = true;
2577 pi->caps_vce_pg = false; /* XXX true */
2578 pi->caps_samu_pg = false;
2579 pi->caps_acp_pg = false;
2580 pi->caps_stable_p_state = false;
2593 pi->enable_dpm = true;
2601 struct kv_power_info *pi = kv_get_pi(rdev);
2611 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);
2615 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");
2616 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en");
2624 struct kv_power_info *pi = kv_get_pi(rdev);
2633 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);
2640 struct kv_power_info *pi = kv_get_pi(rdev);
2642 return pi->sys_info.bootup_uma_clk;
2682 struct kv_power_info *pi = kv_get_pi(rdev);
2683 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps);
2693 struct kv_power_info *pi = kv_get_pi(rdev);
2695 return pi->sys_info.bootup_uma_clk;