Lines Matching defs:rdev
37 static int kv_enable_nb_dpm(struct radeon_device *rdev,
39 static void kv_init_graphics_levels(struct radeon_device *rdev);
40 static int kv_calculate_ds_divider(struct radeon_device *rdev);
41 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev);
42 static int kv_calculate_dpm_settings(struct radeon_device *rdev);
43 static void kv_enable_new_levels(struct radeon_device *rdev);
44 static void kv_program_nbps_index_settings(struct radeon_device *rdev,
46 static int kv_set_enabled_level(struct radeon_device *rdev, u32 level);
47 static int kv_set_enabled_levels(struct radeon_device *rdev);
48 static int kv_force_dpm_highest(struct radeon_device *rdev);
49 static int kv_force_dpm_lowest(struct radeon_device *rdev);
50 static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
53 static int kv_set_thermal_temperature_range(struct radeon_device *rdev,
55 static int kv_init_fps_limits(struct radeon_device *rdev);
57 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
58 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate);
59 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate);
60 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate);
62 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
63 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
64 extern void cik_update_cg(struct radeon_device *rdev,
151 static struct kv_power_info *kv_get_pi(struct radeon_device *rdev)
153 struct kv_power_info *pi = rdev->pm.dpm.priv;
158 static int kv_program_pt_config_registers(struct radeon_device *rdev,
207 static void kv_do_enable_didt(struct radeon_device *rdev, bool enable)
209 struct kv_power_info *pi = kv_get_pi(rdev);
249 static int kv_enable_didt(struct radeon_device *rdev, bool enable)
251 struct kv_power_info *pi = kv_get_pi(rdev);
258 cik_enter_rlc_safe_mode(rdev);
261 ret = kv_program_pt_config_registers(rdev, didt_config_kv);
263 cik_exit_rlc_safe_mode(rdev);
268 kv_do_enable_didt(rdev, enable);
270 cik_exit_rlc_safe_mode(rdev);
276 static int kv_enable_smc_cac(struct radeon_device *rdev, bool enable)
278 struct kv_power_info *pi = kv_get_pi(rdev);
283 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_EnableCac);
289 kv_notify_message_to_smu(rdev, PPSMC_MSG_DisableCac);
297 static int kv_process_firmware_header(struct radeon_device *rdev)
299 struct kv_power_info *pi = kv_get_pi(rdev);
303 ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION +
310 ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION +
320 static int kv_enable_dpm_voltage_scaling(struct radeon_device *rdev)
322 struct kv_power_info *pi = kv_get_pi(rdev);
327 ret = kv_copy_bytes_to_smc(rdev,
336 static int kv_set_dpm_interval(struct radeon_device *rdev)
338 struct kv_power_info *pi = kv_get_pi(rdev);
343 ret = kv_copy_bytes_to_smc(rdev,
352 static int kv_set_dpm_boot_state(struct radeon_device *rdev)
354 struct kv_power_info *pi = kv_get_pi(rdev);
357 ret = kv_copy_bytes_to_smc(rdev,
366 static void kv_program_vc(struct radeon_device *rdev)
371 static void kv_clear_vc(struct radeon_device *rdev)
376 static int kv_set_divider_value(struct radeon_device *rdev,
379 struct kv_power_info *pi = kv_get_pi(rdev);
383 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
394 static u32 kv_convert_vid2_to_vid7(struct radeon_device *rdev,
399 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
416 static u32 kv_convert_vid7_to_vid2(struct radeon_device *rdev,
421 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
440 static u16 kv_convert_8bit_index_to_voltage(struct radeon_device *rdev,
446 static u16 kv_convert_2bit_index_to_voltage(struct radeon_device *rdev,
449 struct kv_power_info *pi = kv_get_pi(rdev);
450 u32 vid_8bit = kv_convert_vid2_to_vid7(rdev,
454 return kv_convert_8bit_index_to_voltage(rdev, (u16)vid_8bit);
458 static int kv_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
460 struct kv_power_info *pi = kv_get_pi(rdev);
464 cpu_to_be32(kv_convert_2bit_index_to_voltage(rdev, vid));
469 static int kv_set_at(struct radeon_device *rdev, u32 index, u32 at)
471 struct kv_power_info *pi = kv_get_pi(rdev);
478 static void kv_dpm_power_level_enable(struct radeon_device *rdev,
481 struct kv_power_info *pi = kv_get_pi(rdev);
486 static void kv_start_dpm(struct radeon_device *rdev)
493 kv_smc_dpm_enable(rdev, true);
496 static void kv_stop_dpm(struct radeon_device *rdev)
498 kv_smc_dpm_enable(rdev, false);
501 static void kv_start_am(struct radeon_device *rdev)
511 static void kv_reset_am(struct radeon_device *rdev)
520 static int kv_freeze_sclk_dpm(struct radeon_device *rdev, bool freeze)
522 return kv_notify_message_to_smu(rdev, freeze ?
526 static int kv_force_lowest_valid(struct radeon_device *rdev)
528 return kv_force_dpm_lowest(rdev);
531 static int kv_unforce_levels(struct radeon_device *rdev)
533 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
534 return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel);
536 return kv_set_enabled_levels(rdev);
539 static int kv_update_sclk_t(struct radeon_device *rdev)
541 struct kv_power_info *pi = kv_get_pi(rdev);
548 ret = kv_copy_bytes_to_smc(rdev,
557 static int kv_program_bootup_state(struct radeon_device *rdev)
559 struct kv_power_info *pi = kv_get_pi(rdev);
562 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
571 kv_dpm_power_level_enable(rdev, i, true);
585 kv_dpm_power_level_enable(rdev, i, true);
590 static int kv_enable_auto_thermal_throttling(struct radeon_device *rdev)
592 struct kv_power_info *pi = kv_get_pi(rdev);
597 ret = kv_copy_bytes_to_smc(rdev,
606 static int kv_upload_dpm_settings(struct radeon_device *rdev)
608 struct kv_power_info *pi = kv_get_pi(rdev);
611 ret = kv_copy_bytes_to_smc(rdev,
621 ret = kv_copy_bytes_to_smc(rdev,
635 static u32 kv_get_clk_bypass(struct radeon_device *rdev, u32 clk)
637 struct kv_power_info *pi = kv_get_pi(rdev);
660 static int kv_populate_uvd_table(struct radeon_device *rdev)
662 struct kv_power_info *pi = kv_get_pi(rdev);
664 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
683 (u8)kv_get_clk_bypass(rdev, table->entries[i].vclk);
685 (u8)kv_get_clk_bypass(rdev, table->entries[i].dclk);
687 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
693 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
702 ret = kv_copy_bytes_to_smc(rdev,
712 ret = kv_copy_bytes_to_smc(rdev,
720 ret = kv_copy_bytes_to_smc(rdev,
731 static int kv_populate_vce_table(struct radeon_device *rdev)
733 struct kv_power_info *pi = kv_get_pi(rdev);
737 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
753 (u8)kv_get_clk_bypass(rdev, table->entries[i].evclk);
755 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
764 ret = kv_copy_bytes_to_smc(rdev,
775 ret = kv_copy_bytes_to_smc(rdev,
784 ret = kv_copy_bytes_to_smc(rdev,
794 static int kv_populate_samu_table(struct radeon_device *rdev)
796 struct kv_power_info *pi = kv_get_pi(rdev);
798 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
816 (u8)kv_get_clk_bypass(rdev, table->entries[i].clk);
818 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
827 ret = kv_copy_bytes_to_smc(rdev,
838 ret = kv_copy_bytes_to_smc(rdev,
847 ret = kv_copy_bytes_to_smc(rdev,
860 static int kv_populate_acp_table(struct radeon_device *rdev)
862 struct kv_power_info *pi = kv_get_pi(rdev);
864 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
877 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
886 ret = kv_copy_bytes_to_smc(rdev,
897 ret = kv_copy_bytes_to_smc(rdev,
906 ret = kv_copy_bytes_to_smc(rdev,
918 static void kv_calculate_dfs_bypass_settings(struct radeon_device *rdev)
920 struct kv_power_info *pi = kv_get_pi(rdev);
923 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
968 static int kv_enable_ulv(struct radeon_device *rdev, bool enable)
970 return kv_notify_message_to_smu(rdev, enable ?
974 static void kv_reset_acp_boot_level(struct radeon_device *rdev)
976 struct kv_power_info *pi = kv_get_pi(rdev);
981 static void kv_update_current_ps(struct radeon_device *rdev,
985 struct kv_power_info *pi = kv_get_pi(rdev);
992 static void kv_update_requested_ps(struct radeon_device *rdev,
996 struct kv_power_info *pi = kv_get_pi(rdev);
1003 void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable)
1005 struct kv_power_info *pi = kv_get_pi(rdev);
1009 ret = kv_smc_bapm_enable(rdev, enable);
1015 static void kv_enable_thermal_int(struct radeon_device *rdev, bool enable)
1028 int kv_dpm_enable(struct radeon_device *rdev)
1030 struct kv_power_info *pi = kv_get_pi(rdev);
1033 ret = kv_process_firmware_header(rdev);
1038 kv_init_fps_limits(rdev);
1039 kv_init_graphics_levels(rdev);
1040 ret = kv_program_bootup_state(rdev);
1045 kv_calculate_dfs_bypass_settings(rdev);
1046 ret = kv_upload_dpm_settings(rdev);
1051 ret = kv_populate_uvd_table(rdev);
1056 ret = kv_populate_vce_table(rdev);
1061 ret = kv_populate_samu_table(rdev);
1066 ret = kv_populate_acp_table(rdev);
1071 kv_program_vc(rdev);
1073 kv_start_am(rdev);
1075 ret = kv_enable_auto_thermal_throttling(rdev);
1081 ret = kv_enable_dpm_voltage_scaling(rdev);
1086 ret = kv_set_dpm_interval(rdev);
1091 ret = kv_set_dpm_boot_state(rdev);
1096 ret = kv_enable_ulv(rdev, true);
1101 kv_start_dpm(rdev);
1102 ret = kv_enable_didt(rdev, true);
1107 ret = kv_enable_smc_cac(rdev, true);
1113 kv_reset_acp_boot_level(rdev);
1115 ret = kv_smc_bapm_enable(rdev, false);
1121 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1126 int kv_dpm_late_enable(struct radeon_device *rdev)
1130 if (rdev->irq.installed &&
1131 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1132 ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1137 kv_enable_thermal_int(rdev, true);
1141 kv_dpm_powergate_acp(rdev, true);
1142 kv_dpm_powergate_samu(rdev, true);
1143 kv_dpm_powergate_vce(rdev, true);
1144 kv_dpm_powergate_uvd(rdev, true);
1149 void kv_dpm_disable(struct radeon_device *rdev)
1151 kv_smc_bapm_enable(rdev, false);
1153 if (rdev->family == CHIP_MULLINS)
1154 kv_enable_nb_dpm(rdev, false);
1157 kv_dpm_powergate_acp(rdev, false);
1158 kv_dpm_powergate_samu(rdev, false);
1159 kv_dpm_powergate_vce(rdev, false);
1160 kv_dpm_powergate_uvd(rdev, false);
1162 kv_enable_smc_cac(rdev, false);
1163 kv_enable_didt(rdev, false);
1164 kv_clear_vc(rdev);
1165 kv_stop_dpm(rdev);
1166 kv_enable_ulv(rdev, false);
1167 kv_reset_am(rdev);
1168 kv_enable_thermal_int(rdev, false);
1170 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1173 static void kv_init_sclk_t(struct radeon_device *rdev)
1175 struct kv_power_info *pi = kv_get_pi(rdev);
1180 static int kv_init_fps_limits(struct radeon_device *rdev)
1182 struct kv_power_info *pi = kv_get_pi(rdev);
1190 ret = kv_copy_bytes_to_smc(rdev,
1199 ret = kv_copy_bytes_to_smc(rdev,
1209 static void kv_init_powergate_state(struct radeon_device *rdev)
1211 struct kv_power_info *pi = kv_get_pi(rdev);
1220 static int kv_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
1222 return kv_notify_message_to_smu(rdev, enable ?
1226 static int kv_enable_vce_dpm(struct radeon_device *rdev, bool enable)
1228 return kv_notify_message_to_smu(rdev, enable ?
1232 static int kv_enable_samu_dpm(struct radeon_device *rdev, bool enable)
1234 return kv_notify_message_to_smu(rdev, enable ?
1238 static int kv_enable_acp_dpm(struct radeon_device *rdev, bool enable)
1240 return kv_notify_message_to_smu(rdev, enable ?
1244 static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate)
1246 struct kv_power_info *pi = kv_get_pi(rdev);
1248 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1264 ret = kv_copy_bytes_to_smc(rdev,
1272 kv_send_msg_to_smc_with_parameter(rdev,
1277 return kv_enable_uvd_dpm(rdev, !gate);
1280 static u8 kv_get_vce_boot_level(struct radeon_device *rdev, u32 evclk)
1284 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1294 static int kv_update_vce_dpm(struct radeon_device *rdev,
1298 struct kv_power_info *pi = kv_get_pi(rdev);
1300 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1304 kv_dpm_powergate_vce(rdev, false);
1306 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
1310 pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk);
1312 ret = kv_copy_bytes_to_smc(rdev,
1322 kv_send_msg_to_smc_with_parameter(rdev,
1326 kv_enable_vce_dpm(rdev, true);
1328 kv_enable_vce_dpm(rdev, false);
1330 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);
1331 kv_dpm_powergate_vce(rdev, true);
1337 static int kv_update_samu_dpm(struct radeon_device *rdev, bool gate)
1339 struct kv_power_info *pi = kv_get_pi(rdev);
1341 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1350 ret = kv_copy_bytes_to_smc(rdev,
1360 kv_send_msg_to_smc_with_parameter(rdev,
1365 return kv_enable_samu_dpm(rdev, !gate);
1368 static u8 kv_get_acp_boot_level(struct radeon_device *rdev)
1372 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1385 static void kv_update_acp_boot_level(struct radeon_device *rdev)
1387 struct kv_power_info *pi = kv_get_pi(rdev);
1391 acp_boot_level = kv_get_acp_boot_level(rdev);
1394 kv_send_msg_to_smc_with_parameter(rdev,
1401 static int kv_update_acp_dpm(struct radeon_device *rdev, bool gate)
1403 struct kv_power_info *pi = kv_get_pi(rdev);
1405 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1412 pi->acp_boot_level = kv_get_acp_boot_level(rdev);
1414 ret = kv_copy_bytes_to_smc(rdev,
1424 kv_send_msg_to_smc_with_parameter(rdev,
1429 return kv_enable_acp_dpm(rdev, !gate);
1432 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
1434 struct kv_power_info *pi = kv_get_pi(rdev);
1443 uvd_v1_0_stop(rdev);
1444 cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, false);
1446 kv_update_uvd_dpm(rdev, gate);
1448 kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerOFF);
1451 kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerON);
1452 uvd_v4_2_resume(rdev);
1453 uvd_v1_0_start(rdev);
1454 cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, true);
1456 kv_update_uvd_dpm(rdev, gate);
1460 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate)
1462 struct kv_power_info *pi = kv_get_pi(rdev);
1472 kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerOFF);
1476 kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerON);
1477 vce_v2_0_resume(rdev);
1478 vce_v1_0_start(rdev);
1483 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate)
1485 struct kv_power_info *pi = kv_get_pi(rdev);
1493 kv_update_samu_dpm(rdev, true);
1495 kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerOFF);
1498 kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerON);
1499 kv_update_samu_dpm(rdev, false);
1503 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate)
1505 struct kv_power_info *pi = kv_get_pi(rdev);
1510 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
1516 kv_update_acp_dpm(rdev, true);
1518 kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerOFF);
1521 kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerON);
1522 kv_update_acp_dpm(rdev, false);
1526 static void kv_set_valid_clock_range(struct radeon_device *rdev,
1530 struct kv_power_info *pi = kv_get_pi(rdev);
1533 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1588 static int kv_update_dfs_bypass_settings(struct radeon_device *rdev,
1592 struct kv_power_info *pi = kv_get_pi(rdev);
1599 ret = kv_copy_bytes_to_smc(rdev,
1611 static int kv_enable_nb_dpm(struct radeon_device *rdev,
1614 struct kv_power_info *pi = kv_get_pi(rdev);
1619 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable);
1625 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Disable);
1634 int kv_dpm_force_performance_level(struct radeon_device *rdev,
1640 ret = kv_force_dpm_highest(rdev);
1644 ret = kv_force_dpm_lowest(rdev);
1648 ret = kv_unforce_levels(rdev);
1653 rdev->pm.dpm.forced_level = level;
1658 int kv_dpm_pre_set_power_state(struct radeon_device *rdev)
1660 struct kv_power_info *pi = kv_get_pi(rdev);
1661 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1664 kv_update_requested_ps(rdev, new_ps);
1666 kv_apply_state_adjust_rules(rdev,
1673 int kv_dpm_set_power_state(struct radeon_device *rdev)
1675 struct kv_power_info *pi = kv_get_pi(rdev);
1681 ret = kv_smc_bapm_enable(rdev, rdev->pm.dpm.ac_power);
1688 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
1690 kv_set_valid_clock_range(rdev, new_ps);
1691 kv_update_dfs_bypass_settings(rdev, new_ps);
1692 ret = kv_calculate_ds_divider(rdev);
1697 kv_calculate_nbps_level_settings(rdev);
1698 kv_calculate_dpm_settings(rdev);
1699 kv_force_lowest_valid(rdev);
1700 kv_enable_new_levels(rdev);
1701 kv_upload_dpm_settings(rdev);
1702 kv_program_nbps_index_settings(rdev, new_ps);
1703 kv_unforce_levels(rdev);
1704 kv_set_enabled_levels(rdev);
1705 kv_force_lowest_valid(rdev);
1706 kv_unforce_levels(rdev);
1708 ret = kv_update_vce_dpm(rdev, new_ps, old_ps);
1713 kv_update_sclk_t(rdev);
1714 if (rdev->family == CHIP_MULLINS)
1715 kv_enable_nb_dpm(rdev, true);
1719 kv_set_valid_clock_range(rdev, new_ps);
1720 kv_update_dfs_bypass_settings(rdev, new_ps);
1721 ret = kv_calculate_ds_divider(rdev);
1726 kv_calculate_nbps_level_settings(rdev);
1727 kv_calculate_dpm_settings(rdev);
1728 kv_freeze_sclk_dpm(rdev, true);
1729 kv_upload_dpm_settings(rdev);
1730 kv_program_nbps_index_settings(rdev, new_ps);
1731 kv_freeze_sclk_dpm(rdev, false);
1732 kv_set_enabled_levels(rdev);
1733 ret = kv_update_vce_dpm(rdev, new_ps, old_ps);
1738 kv_update_acp_boot_level(rdev);
1739 kv_update_sclk_t(rdev);
1740 kv_enable_nb_dpm(rdev, true);
1747 void kv_dpm_post_set_power_state(struct radeon_device *rdev)
1749 struct kv_power_info *pi = kv_get_pi(rdev);
1752 kv_update_current_ps(rdev, new_ps);
1755 void kv_dpm_setup_asic(struct radeon_device *rdev)
1757 sumo_take_smu_control(rdev, true);
1758 kv_init_powergate_state(rdev);
1759 kv_init_sclk_t(rdev);
1764 static void kv_construct_max_power_limits_table(struct radeon_device *rdev,
1767 struct kv_power_info *pi = kv_get_pi(rdev);
1774 kv_convert_2bit_index_to_voltage(rdev,
1781 static void kv_patch_voltage_values(struct radeon_device *rdev)
1785 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1787 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1789 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1791 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1796 kv_convert_8bit_index_to_voltage(rdev,
1803 kv_convert_8bit_index_to_voltage(rdev,
1810 kv_convert_8bit_index_to_voltage(rdev,
1817 kv_convert_8bit_index_to_voltage(rdev,
1823 static void kv_construct_boot_state(struct radeon_device *rdev)
1825 struct kv_power_info *pi = kv_get_pi(rdev);
1837 static int kv_force_dpm_highest(struct radeon_device *rdev)
1842 ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
1851 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
1852 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
1854 return kv_set_enabled_level(rdev, i);
1857 static int kv_force_dpm_lowest(struct radeon_device *rdev)
1862 ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
1871 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
1872 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
1874 return kv_set_enabled_level(rdev, i);
1877 static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
1880 struct kv_power_info *pi = kv_get_pi(rdev);
1901 static int kv_get_high_voltage_limit(struct radeon_device *rdev, int *limit)
1903 struct kv_power_info *pi = kv_get_pi(rdev);
1905 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1911 (kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v) <=
1923 (kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit) <=
1935 static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
1940 struct kv_power_info *pi = kv_get_pi(rdev);
1946 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1949 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
1952 new_rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
1953 new_rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
1979 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
1980 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
1994 kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
1995 kv_get_high_voltage_limit(rdev, &limit);
2006 kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
2007 kv_get_high_voltage_limit(rdev, &limit);
2028 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
2041 pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) ||
2051 static void kv_dpm_power_level_enabled_for_throttle(struct radeon_device *rdev,
2054 struct kv_power_info *pi = kv_get_pi(rdev);
2059 static int kv_calculate_ds_divider(struct radeon_device *rdev)
2061 struct kv_power_info *pi = kv_get_pi(rdev);
2070 kv_get_sleep_divider_id_from_clock(rdev,
2077 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev)
2079 struct kv_power_info *pi = kv_get_pi(rdev);
2083 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2089 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
2100 (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);
2131 static int kv_calculate_dpm_settings(struct radeon_device *rdev)
2133 struct kv_power_info *pi = kv_get_pi(rdev);
2145 static void kv_init_graphics_levels(struct radeon_device *rdev)
2147 struct kv_power_info *pi = kv_get_pi(rdev);
2150 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2159 kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v)))
2162 kv_set_divider_value(rdev, i, table->entries[i].clk);
2163 vid_2bit = kv_convert_vid7_to_vid2(rdev,
2166 kv_set_vid(rdev, i, vid_2bit);
2167 kv_set_at(rdev, i, pi->at[i]);
2168 kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
2179 kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit))
2182 kv_set_divider_value(rdev, i, table->entries[i].sclk_frequency);
2183 kv_set_vid(rdev, i, table->entries[i].vid_2bit);
2184 kv_set_at(rdev, i, pi->at[i]);
2185 kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
2191 kv_dpm_power_level_enable(rdev, i, false);
2194 static void kv_enable_new_levels(struct radeon_device *rdev)
2196 struct kv_power_info *pi = kv_get_pi(rdev);
2201 kv_dpm_power_level_enable(rdev, i, true);
2205 static int kv_set_enabled_level(struct radeon_device *rdev, u32 level)
2209 return kv_send_msg_to_smc_with_parameter(rdev,
2214 static int kv_set_enabled_levels(struct radeon_device *rdev)
2216 struct kv_power_info *pi = kv_get_pi(rdev);
2222 return kv_send_msg_to_smc_with_parameter(rdev,
2227 static void kv_program_nbps_index_settings(struct radeon_device *rdev,
2231 struct kv_power_info *pi = kv_get_pi(rdev);
2234 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
2249 static int kv_set_thermal_temperature_range(struct radeon_device *rdev,
2271 rdev->pm.dpm.thermal.min_temp = low_temp;
2272 rdev->pm.dpm.thermal.max_temp = high_temp;
2286 static int kv_parse_sys_info_table(struct radeon_device *rdev)
2288 struct kv_power_info *pi = kv_get_pi(rdev);
2289 struct radeon_mode_info *mode_info = &rdev->mode_info;
2336 sumo_construct_sclk_voltage_mapping_table(rdev,
2340 sumo_construct_vid_mapping_table(rdev,
2344 kv_construct_max_power_limits_table(rdev,
2345 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
2371 static void kv_patch_boot_state(struct radeon_device *rdev,
2374 struct kv_power_info *pi = kv_get_pi(rdev);
2380 static void kv_parse_pplib_non_clock_info(struct radeon_device *rdev,
2400 rdev->pm.dpm.boot_ps = rps;
2401 kv_patch_boot_state(rdev, ps);
2404 rdev->pm.dpm.uvd_ps = rps;
2407 static void kv_parse_pplib_clock_info(struct radeon_device *rdev,
2411 struct kv_power_info *pi = kv_get_pi(rdev);
2429 static int kv_parse_power_table(struct radeon_device *rdev)
2431 struct radeon_mode_info *mode_info = &rdev->mode_info;
2461 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
2464 if (!rdev->pm.dpm.ps)
2473 if (!rdev->pm.power_state[i].clock_info)
2477 kfree(rdev->pm.dpm.ps);
2480 rdev->pm.dpm.ps[i].ps_priv = ps;
2492 kv_parse_pplib_clock_info(rdev,
2493 &rdev->pm.dpm.ps[i], k,
2497 kv_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
2502 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
2507 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
2512 rdev->pm.dpm.vce_states[i].sclk = sclk;
2513 rdev->pm.dpm.vce_states[i].mclk = 0;
2519 int kv_dpm_init(struct radeon_device *rdev)
2527 rdev->pm.dpm.priv = pi;
2529 ret = r600_get_platform_caps(rdev);
2533 ret = r600_parse_extended_power_table(rdev);
2543 if (rdev->pdev->subsystem_vendor == 0x1849)
2563 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
2582 ret = kv_parse_sys_info_table(rdev);
2586 kv_patch_voltage_values(rdev);
2587 kv_construct_boot_state(rdev);
2589 ret = kv_parse_power_table(rdev);
2598 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
2601 struct kv_power_info *pi = kv_get_pi(rdev);
2614 vddc = kv_convert_8bit_index_to_voltage(rdev, (u16)tmp);
2622 u32 kv_dpm_get_current_sclk(struct radeon_device *rdev)
2624 struct kv_power_info *pi = kv_get_pi(rdev);
2638 u32 kv_dpm_get_current_mclk(struct radeon_device *rdev)
2640 struct kv_power_info *pi = kv_get_pi(rdev);
2645 void kv_dpm_print_power_state(struct radeon_device *rdev,
2658 kv_convert_8bit_index_to_voltage(rdev, pl->vddc_index));
2660 r600_dpm_print_ps_status(rdev, rps);
2663 void kv_dpm_fini(struct radeon_device *rdev)
2667 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2668 kfree(rdev->pm.dpm.ps[i].ps_priv);
2670 kfree(rdev->pm.dpm.ps);
2671 kfree(rdev->pm.dpm.priv);
2672 r600_free_extended_power_table(rdev);
2675 void kv_dpm_display_configuration_changed(struct radeon_device *rdev)
2680 u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low)
2682 struct kv_power_info *pi = kv_get_pi(rdev);
2691 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low)
2693 struct kv_power_info *pi = kv_get_pi(rdev);