Lines Matching defs:offset
68 void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset,
81 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
84 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
88 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));
89 WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);
91 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz));
92 WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz);
94 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz));
95 WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz);
209 void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset,
214 WREG32(AFMT_AVI_INFO0 + offset,
216 WREG32(AFMT_AVI_INFO1 + offset,
218 WREG32(AFMT_AVI_INFO2 + offset,
220 WREG32(AFMT_AVI_INFO3 + offset,
223 WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
307 void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset)
312 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
318 void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc)
325 val = RREG32(HDMI_CONTROL + offset);
352 WREG32(HDMI_CONTROL + offset, val);
355 void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset)
360 WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
363 WREG32(AFMT_60958_0 + offset,
366 WREG32(AFMT_60958_1 + offset,
369 WREG32(AFMT_60958_2 + offset,
377 WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
380 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
385 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
390 void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
396 WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE);
398 WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE);
415 WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,
420 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
423 WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,
426 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
430 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
432 WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0);
438 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
459 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
462 WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset,
467 val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset);
475 WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val);
478 WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset,
484 WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0);
485 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,