Lines Matching defs:reloc
1057 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1096 struct radeon_bo_list *reloc;
1142 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1148 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1171 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1179 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1180 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1181 if (reloc->tiling_flags & RADEON_TILING_MACRO) {
1184 evergreen_tiling_fields(reloc->tiling_flags,
1213 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1220 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1221 track->db_z_read_bo = reloc->robj;
1225 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1232 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1233 track->db_z_write_bo = reloc->robj;
1237 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1244 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1245 track->db_s_read_bo = reloc->robj;
1249 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1256 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1257 track->db_s_write_bo = reloc->robj;
1272 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1280 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1281 track->vgt_strmout_bo[tmp] = reloc->robj;
1294 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1296 dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1300 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1359 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1365 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1366 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1377 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1383 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1384 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1438 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1445 if (reloc->tiling_flags & RADEON_TILING_MACRO) {
1448 evergreen_tiling_fields(reloc->tiling_flags,
1466 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1473 if (reloc->tiling_flags & RADEON_TILING_MACRO) {
1476 evergreen_tiling_fields(reloc->tiling_flags,
1499 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1504 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1505 track->cb_color_fmask_bo[tmp] = reloc->robj;
1516 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1521 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1522 track->cb_color_cmask_bo[tmp] = reloc->robj;
1554 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1562 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1563 track->cb_color_bo[tmp] = reloc->robj;
1570 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1578 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1579 track->cb_color_bo[tmp] = reloc->robj;
1583 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1590 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1591 track->htile_bo = reloc->robj;
1701 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1707 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1715 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1721 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1729 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1735 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1774 struct radeon_bo_list *reloc;
1812 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1818 offset = reloc->gpu_offset +
1858 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1864 offset = reloc->gpu_offset +
1893 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1899 offset = reloc->gpu_offset +
1921 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1927 offset = reloc->gpu_offset +
2016 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2022 track->indirect_draw_buffer_size = radeon_bo_size(reloc->robj);
2024 ib[idx+1] = reloc->gpu_offset;
2025 ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff;
2073 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2078 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff);
2094 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2100 offset = reloc->gpu_offset +
2148 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2157 offset = reloc->gpu_offset + tmp;
2159 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
2161 tmp + size, radeon_bo_size(reloc->robj));
2186 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2195 offset = reloc->gpu_offset + tmp;
2197 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
2199 tmp + size, radeon_bo_size(reloc->robj));
2226 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2231 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
2242 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2247 offset = reloc->gpu_offset +
2263 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2269 offset = reloc->gpu_offset +
2285 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2291 offset = reloc->gpu_offset +
2354 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2361 TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
2362 if (reloc->tiling_flags & RADEON_TILING_MACRO) {
2365 evergreen_tiling_fields(reloc->tiling_flags,
2376 texture = reloc->robj;
2377 toffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
2391 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2396 moffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
2397 mipmap = reloc->robj;
2410 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2417 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2420 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset;
2423 offset64 = reloc->gpu_offset + offset;
2492 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2494 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2499 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2501 offset + 4, radeon_bo_size(reloc->robj));
2504 offset += reloc->gpu_offset;
2511 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2513 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2518 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2520 offset + 4, radeon_bo_size(reloc->robj));
2523 offset += reloc->gpu_offset;
2536 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2538 DRM_ERROR("bad MEM_WRITE (missing reloc)\n");
2547 if ((offset + 8) > radeon_bo_size(reloc->robj)) {
2549 offset + 8, radeon_bo_size(reloc->robj));
2552 offset += reloc->gpu_offset;
2565 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2567 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2572 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2574 offset + 4, radeon_bo_size(reloc->robj));
2577 offset += reloc->gpu_offset;
2592 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2594 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2599 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2601 offset + 4, radeon_bo_size(reloc->robj));
2604 offset += reloc->gpu_offset;
2642 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2644 DRM_ERROR("bad SET_APPEND_CNT (missing reloc)\n");
2653 offset += reloc->gpu_offset;
2792 * the GPU addresses based on the reloc information and