Lines Matching refs:crtc_offsets
122 static const u32 crtc_offsets[6] =
1349 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
1359 pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
1360 pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
1383 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))
2681 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
2685 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
2688 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2690 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
2691 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
2694 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
2697 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2699 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
2700 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
2722 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2723 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
2725 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
2726 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
2750 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
2753 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
2755 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
2758 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
2771 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
2773 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
2775 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
2777 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
2789 tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
2792 WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
2794 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
2797 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
2799 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
2802 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
2805 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
2823 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
2825 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2826 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
2827 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
2829 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
2831 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2832 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
2833 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
3806 if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN) {
3807 crtc_status[i] = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
3815 tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
4457 return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
4479 WREG32(INT_MASK + crtc_offsets[i], 0);
4481 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0);
4579 rdev, INT_MASK + crtc_offsets[i],
4586 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK);
4602 rdev, AFMT_AUDIO_PACKET_CONTROL + crtc_offsets[i],
4623 afmt_status[i] = RREG32(AFMT_STATUS + crtc_offsets[i]);
4625 grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]);
4632 WREG32(GRPH_INT_STATUS + crtc_offsets[j],
4638 WREG32(VBLANK_STATUS + crtc_offsets[j],
4641 WREG32(VLINE_STATUS + crtc_offsets[j],
4658 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + crtc_offsets[i],