Lines Matching defs:ring
2934 struct radeon_ring *ring = &rdev->ring[ib->ring];
2938 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
2939 radeon_ring_write(ring, 1);
2941 if (ring->rptr_save_reg) {
2942 next_rptr = ring->wptr + 3 + 4;
2943 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2944 radeon_ring_write(ring, ((ring->rptr_save_reg -
2946 radeon_ring_write(ring, next_rptr);
2948 next_rptr = ring->wptr + 5 + 4;
2949 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
2950 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2951 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
2952 radeon_ring_write(ring, next_rptr);
2953 radeon_ring_write(ring, 0);
2956 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2957 radeon_ring_write(ring,
2962 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
2963 radeon_ring_write(ring, ib->length_dw);
3001 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3005 r = radeon_ring_lock(rdev, ring, 7);
3007 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3010 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
3011 radeon_ring_write(ring, 0x1);
3012 radeon_ring_write(ring, 0x0);
3013 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
3014 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
3015 radeon_ring_write(ring, 0);
3016 radeon_ring_write(ring, 0);
3017 radeon_ring_unlock_commit(rdev, ring, false);
3022 r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
3024 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3029 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3030 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3033 radeon_ring_write(ring, evergreen_default_state[i]);
3035 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3036 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3039 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3040 radeon_ring_write(ring, 0);
3043 radeon_ring_write(ring, 0xc0026f00);
3044 radeon_ring_write(ring, 0x00000000);
3045 radeon_ring_write(ring, 0x00000000);
3046 radeon_ring_write(ring, 0x00000000);
3049 radeon_ring_write(ring, 0xc0036f00);
3050 radeon_ring_write(ring, 0x00000bc4);
3051 radeon_ring_write(ring, 0xffffffff);
3052 radeon_ring_write(ring, 0xffffffff);
3053 radeon_ring_write(ring, 0xffffffff);
3055 radeon_ring_write(ring, 0xc0026900);
3056 radeon_ring_write(ring, 0x00000316);
3057 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
3058 radeon_ring_write(ring, 0x00000010); /* */
3060 radeon_ring_unlock_commit(rdev, ring, false);
3067 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3084 /* Set ring buffer size */
3085 rb_bufsz = order_base_2(ring->ring_size / 8);
3097 /* Initialize the ring buffer's read and write pointers */
3100 ring->wptr = 0;
3101 WREG32(CP_RB_WPTR, ring->wptr);
3119 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
3123 ring->ready = true;
3124 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
3126 ring->ready = false;
4088 * @ring: radeon_ring structure holding ring information
4093 bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
4100 radeon_ring_lockup_update(rdev, ring);
4103 return radeon_ring_test_lockup(rdev, ring);
4689 /* When a ring buffer overflow happen start parsing interrupt
4693 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
4733 /* Order reading of wptr vs. reading of IH ring data */
4742 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
4743 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
4860 case 176: /* CP_INT in ring buffer */
4954 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
4955 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
4978 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
4983 struct radeon_ring *ring;
4986 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
4989 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
4990 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
4992 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
5004 struct radeon_ring *ring;
5083 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
5084 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
5089 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
5090 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
5256 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
5257 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
5259 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
5260 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);