Lines Matching defs:rdev
56 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
61 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
64 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
68 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
72 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
75 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
78 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
83 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
86 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
90 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
94 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
97 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
100 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
105 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
108 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
112 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
116 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
119 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
219 static void evergreen_gpu_init(struct radeon_device *rdev);
220 void evergreen_fini(struct radeon_device *rdev);
221 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
222 void evergreen_program_aspm(struct radeon_device *rdev);
996 static void evergreen_init_golden_registers(struct radeon_device *rdev)
998 switch (rdev->family) {
1001 radeon_program_register_sequence(rdev,
1004 radeon_program_register_sequence(rdev,
1007 radeon_program_register_sequence(rdev,
1012 radeon_program_register_sequence(rdev,
1015 radeon_program_register_sequence(rdev,
1018 radeon_program_register_sequence(rdev,
1023 radeon_program_register_sequence(rdev,
1026 radeon_program_register_sequence(rdev,
1029 radeon_program_register_sequence(rdev,
1034 radeon_program_register_sequence(rdev,
1037 radeon_program_register_sequence(rdev,
1040 radeon_program_register_sequence(rdev,
1045 radeon_program_register_sequence(rdev,
1050 radeon_program_register_sequence(rdev,
1055 radeon_program_register_sequence(rdev,
1058 radeon_program_register_sequence(rdev,
1063 radeon_program_register_sequence(rdev,
1068 radeon_program_register_sequence(rdev,
1073 radeon_program_register_sequence(rdev,
1085 * @rdev: radeon_device pointer
1092 int evergreen_get_allowed_info_register(struct radeon_device *rdev,
1141 static int sumo_set_uvd_clock(struct radeon_device *rdev, u32 clock,
1147 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1165 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
1170 r = sumo_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS);
1176 r = sumo_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS);
1188 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
1208 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
1226 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
1263 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
1277 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
1282 readrq = pcie_get_readrq(rdev->pdev);
1288 pcie_set_readrq(rdev->pdev, 512);
1294 struct radeon_device *rdev = dev->dev_private;
1347 static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)
1355 static bool dce4_is_counter_moving(struct radeon_device *rdev, int crtc)
1371 * @rdev: radeon_device pointer
1376 void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
1380 if (crtc >= rdev->num_crtc)
1389 while (dce4_is_in_vblank(rdev, crtc)) {
1391 if (!dce4_is_counter_moving(rdev, crtc))
1396 while (!dce4_is_in_vblank(rdev, crtc)) {
1398 if (!dce4_is_counter_moving(rdev, crtc))
1407 * @rdev: radeon_device pointer
1415 void evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base,
1418 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
1439 * @rdev: radeon_device pointer
1444 bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc_id)
1446 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
1454 int evergreen_get_temp(struct radeon_device *rdev)
1459 if (rdev->family == CHIP_JUNIPER) {
1492 int sumo_get_temp(struct radeon_device *rdev)
1503 * @rdev: radeon_device pointer
1509 void sumo_pm_init_profile(struct radeon_device *rdev)
1514 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
1515 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
1516 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
1517 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
1520 if (rdev->flags & RADEON_IS_MOBILITY)
1521 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
1523 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
1525 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
1526 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
1527 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
1528 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
1530 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
1531 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
1532 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
1533 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
1535 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
1536 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
1537 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
1538 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
1540 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
1541 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
1542 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
1543 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
1546 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
1547 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
1548 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
1549 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
1550 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
1551 rdev->pm.power_state[idx].num_clock_modes - 1;
1553 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
1554 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
1555 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
1556 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
1557 rdev->pm.power_state[idx].num_clock_modes - 1;
1563 * @rdev: radeon_device pointer
1569 void btc_pm_init_profile(struct radeon_device *rdev)
1574 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
1575 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
1576 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
1577 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
1582 if (rdev->flags & RADEON_IS_MOBILITY)
1583 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
1585 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
1587 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
1588 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
1589 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
1590 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
1592 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
1593 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
1594 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
1595 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
1597 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
1598 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
1599 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
1600 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
1602 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
1603 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
1604 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
1605 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
1607 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
1608 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
1609 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
1610 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
1612 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
1613 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
1614 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
1615 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
1621 * @rdev: radeon_device pointer
1626 void evergreen_pm_misc(struct radeon_device *rdev)
1628 int req_ps_idx = rdev->pm.requested_power_state_index;
1629 int req_cm_idx = rdev->pm.requested_clock_mode_index;
1630 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
1637 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
1638 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
1639 rdev->pm.current_vddc = voltage->voltage;
1647 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
1648 (rdev->family >= CHIP_BARTS) &&
1649 rdev->pm.active_crtc_count &&
1650 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
1651 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
1652 voltage = &rdev->pm.power_state[req_ps_idx].
1653 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].voltage;
1658 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
1659 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
1660 rdev->pm.current_vddci = voltage->vddci;
1669 * @rdev: radeon_device pointer
1673 void evergreen_pm_prepare(struct radeon_device *rdev)
1675 struct drm_device *ddev = rdev->ddev;
1694 * @rdev: radeon_device pointer
1698 void evergreen_pm_finish(struct radeon_device *rdev)
1700 struct drm_device *ddev = rdev->ddev;
1719 * @rdev: radeon_device pointer
1725 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
1736 * @rdev: radeon_device pointer
1741 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
1744 bool connected = evergreen_hpd_sense(rdev, hpd);
1758 * @rdev: radeon_device pointer
1763 void evergreen_hpd_init(struct radeon_device *rdev)
1765 struct drm_device *dev = rdev->ddev;
1791 radeon_hpd_set_polarity(rdev, hpd);
1793 radeon_irq_kms_enable_hpd(rdev, enabled);
1799 * @rdev: radeon_device pointer
1804 void evergreen_hpd_fini(struct radeon_device *rdev)
1806 struct drm_device *dev = rdev->ddev;
1820 radeon_irq_kms_disable_hpd(rdev, disabled);
1825 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
1871 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1874 for (i = 0; i < rdev->usec_timeout; i++) {
1887 if (ASIC_IS_DCE5(rdev))
1893 if (ASIC_IS_DCE5(rdev))
1899 if (ASIC_IS_DCE5(rdev))
1905 if (ASIC_IS_DCE5(rdev))
1916 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
2154 static void evergreen_program_watermarks(struct radeon_device *rdev,
2179 dram_channels = evergreen_get_number_of_dram_channels(rdev);
2182 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
2184 radeon_dpm_get_mclk(rdev, false) * 10;
2186 radeon_dpm_get_sclk(rdev, false) * 10;
2188 wm_high.yclk = rdev->pm.current_mclk * 10;
2189 wm_high.sclk = rdev->pm.current_sclk * 10;
2209 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
2211 radeon_dpm_get_mclk(rdev, true) * 10;
2213 radeon_dpm_get_sclk(rdev, true) * 10;
2215 wm_low.yclk = rdev->pm.current_mclk * 10;
2216 wm_low.sclk = rdev->pm.current_sclk * 10;
2245 (rdev->disp_priority == 2)) {
2252 (rdev->disp_priority == 2)) {
2318 * @rdev: radeon_device pointer
2323 void evergreen_bandwidth_update(struct radeon_device *rdev)
2330 if (!rdev->mode_info.mode_config_initialized)
2333 radeon_update_display_priority(rdev);
2335 for (i = 0; i < rdev->num_crtc; i++) {
2336 if (rdev->mode_info.crtcs[i]->base.enabled)
2339 for (i = 0; i < rdev->num_crtc; i += 2) {
2340 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
2341 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
2342 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
2343 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
2344 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
2345 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
2352 * @rdev: radeon_device pointer
2358 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
2363 for (i = 0; i < rdev->usec_timeout; i++) {
2376 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
2384 for (i = 0; i < rdev->usec_timeout; i++) {
2399 static int evergreen_pcie_gart_enable(struct radeon_device *rdev)
2404 if (rdev->gart.robj == NULL) {
2405 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
2408 r = radeon_gart_table_vram_pin(rdev);
2422 if (rdev->flags & RADEON_IS_IGP) {
2430 if ((rdev->family == CHIP_JUNIPER) ||
2431 (rdev->family == CHIP_CYPRESS) ||
2432 (rdev->family == CHIP_HEMLOCK) ||
2433 (rdev->family == CHIP_BARTS))
2440 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
2441 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
2442 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
2446 (u32)(rdev->dummy_page.addr >> 12));
2449 evergreen_pcie_gart_tlb_flush(rdev);
2451 (unsigned)(rdev->mc.gtt_size >> 20),
2452 (unsigned long long)rdev->gart.table_addr);
2453 rdev->gart.ready = true;
2457 static void evergreen_pcie_gart_disable(struct radeon_device *rdev)
2479 radeon_gart_table_vram_unpin(rdev);
2482 static void evergreen_pcie_gart_fini(struct radeon_device *rdev)
2484 evergreen_pcie_gart_disable(rdev);
2485 radeon_gart_table_vram_free(rdev);
2486 radeon_gart_fini(rdev);
2490 static void evergreen_agp_enable(struct radeon_device *rdev)
2566 static bool evergreen_is_dp_sst_stream_enabled(struct radeon_device *rdev,
2626 static void evergreen_blank_dp_output(struct radeon_device *rdev,
2666 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
2672 if (!ASIC_IS_NODCE(rdev)) {
2680 for (i = 0; i < rdev->num_crtc; i++) {
2684 if (ASIC_IS_DCE6(rdev)) {
2687 radeon_wait_for_vblank(rdev, i);
2696 radeon_wait_for_vblank(rdev, i);
2704 frame_count = radeon_get_vblank_counter(rdev, i);
2705 for (j = 0; j < rdev->usec_timeout; j++) {
2706 if (radeon_get_vblank_counter(rdev, i) != frame_count)
2717 if (ASIC_IS_DCE5(rdev) &&
2718 evergreen_is_dp_sst_stream_enabled(rdev, i ,&dig_fe))
2719 evergreen_blank_dp_output(rdev, dig_fe);
2734 radeon_mc_wait_for_idle(rdev);
2748 for (i = 0; i < rdev->num_crtc; i++) {
2764 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
2770 for (i = 0; i < rdev->num_crtc; i++) {
2772 upper_32_bits(rdev->mc.vram_start));
2774 upper_32_bits(rdev->mc.vram_start));
2776 (u32)rdev->mc.vram_start);
2778 (u32)rdev->mc.vram_start);
2781 if (!ASIC_IS_NODCE(rdev)) {
2782 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
2783 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
2787 for (i = 0; i < rdev->num_crtc; i++) {
2804 for (j = 0; j < rdev->usec_timeout; j++) {
2820 for (i = 0; i < rdev->num_crtc; i++) {
2822 if (ASIC_IS_DCE6(rdev)) {
2836 frame_count = radeon_get_vblank_counter(rdev, i);
2837 for (j = 0; j < rdev->usec_timeout; j++) {
2838 if (radeon_get_vblank_counter(rdev, i) != frame_count)
2844 if (!ASIC_IS_NODCE(rdev)) {
2852 void evergreen_mc_program(struct radeon_device *rdev)
2868 evergreen_mc_stop(rdev, &save);
2869 if (evergreen_mc_wait_for_idle(rdev)) {
2870 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2875 if (rdev->flags & RADEON_IS_AGP) {
2876 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
2879 rdev->mc.vram_start >> 12);
2881 rdev->mc.gtt_end >> 12);
2885 rdev->mc.gtt_start >> 12);
2887 rdev->mc.vram_end >> 12);
2891 rdev->mc.vram_start >> 12);
2893 rdev->mc.vram_end >> 12);
2895 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
2897 if ((rdev->family == CHIP_PALM) ||
2898 (rdev->family == CHIP_SUMO) ||
2899 (rdev->family == CHIP_SUMO2)) {
2901 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
2902 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
2905 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
2906 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
2908 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
2911 if (rdev->flags & RADEON_IS_AGP) {
2912 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
2913 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
2914 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
2920 if (evergreen_mc_wait_for_idle(rdev)) {
2921 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2923 evergreen_mc_resume(rdev, &save);
2926 rv515_vga_render_disable(rdev);
2932 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2934 struct radeon_ring *ring = &rdev->ring[ib->ring];
2947 } else if (rdev->wb.enabled) {
2967 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
2972 if (!rdev->me_fw || !rdev->pfp_fw)
2975 r700_cp_stop(rdev);
2982 fw_data = (const __be32 *)rdev->pfp_fw->data;
2988 fw_data = (const __be32 *)rdev->me_fw->data;
2999 static int evergreen_cp_start(struct radeon_device *rdev)
3001 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3005 r = radeon_ring_lock(rdev, ring, 7);
3013 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
3017 radeon_ring_unlock_commit(rdev, ring, false);
3022 r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
3060 radeon_ring_unlock_commit(rdev, ring, false);
3065 static int evergreen_cp_resume(struct radeon_device *rdev)
3067 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3105 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
3106 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
3107 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
3109 if (rdev->wb.enabled)
3122 evergreen_cp_start(rdev);
3124 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
3135 static void evergreen_gpu_init(struct radeon_device *rdev)
3156 switch (rdev->family) {
3159 rdev->config.evergreen.num_ses = 2;
3160 rdev->config.evergreen.max_pipes = 4;
3161 rdev->config.evergreen.max_tile_pipes = 8;
3162 rdev->config.evergreen.max_simds = 10;
3163 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
3164 rdev->config.evergreen.max_gprs = 256;
3165 rdev->config.evergreen.max_threads = 248;
3166 rdev->config.evergreen.max_gs_threads = 32;
3167 rdev->config.evergreen.max_stack_entries = 512;
3168 rdev->config.evergreen.sx_num_of_sets = 4;
3169 rdev->config.evergreen.sx_max_export_size = 256;
3170 rdev->config.evergreen.sx_max_export_pos_size = 64;
3171 rdev->config.evergreen.sx_max_export_smx_size = 192;
3172 rdev->config.evergreen.max_hw_contexts = 8;
3173 rdev->config.evergreen.sq_num_cf_insts = 2;
3175 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
3176 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3177 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3181 rdev->config.evergreen.num_ses = 1;
3182 rdev->config.evergreen.max_pipes = 4;
3183 rdev->config.evergreen.max_tile_pipes = 4;
3184 rdev->config.evergreen.max_simds = 10;
3185 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
3186 rdev->config.evergreen.max_gprs = 256;
3187 rdev->config.evergreen.max_threads = 248;
3188 rdev->config.evergreen.max_gs_threads = 32;
3189 rdev->config.evergreen.max_stack_entries = 512;
3190 rdev->config.evergreen.sx_num_of_sets = 4;
3191 rdev->config.evergreen.sx_max_export_size = 256;
3192 rdev->config.evergreen.sx_max_export_pos_size = 64;
3193 rdev->config.evergreen.sx_max_export_smx_size = 192;
3194 rdev->config.evergreen.max_hw_contexts = 8;
3195 rdev->config.evergreen.sq_num_cf_insts = 2;
3197 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
3198 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3199 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3203 rdev->config.evergreen.num_ses = 1;
3204 rdev->config.evergreen.max_pipes = 4;
3205 rdev->config.evergreen.max_tile_pipes = 4;
3206 rdev->config.evergreen.max_simds = 5;
3207 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
3208 rdev->config.evergreen.max_gprs = 256;
3209 rdev->config.evergreen.max_threads = 248;
3210 rdev->config.evergreen.max_gs_threads = 32;
3211 rdev->config.evergreen.max_stack_entries = 256;
3212 rdev->config.evergreen.sx_num_of_sets = 4;
3213 rdev->config.evergreen.sx_max_export_size = 256;
3214 rdev->config.evergreen.sx_max_export_pos_size = 64;
3215 rdev->config.evergreen.sx_max_export_smx_size = 192;
3216 rdev->config.evergreen.max_hw_contexts = 8;
3217 rdev->config.evergreen.sq_num_cf_insts = 2;
3219 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
3220 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3221 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3226 rdev->config.evergreen.num_ses = 1;
3227 rdev->config.evergreen.max_pipes = 2;
3228 rdev->config.evergreen.max_tile_pipes = 2;
3229 rdev->config.evergreen.max_simds = 2;
3230 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
3231 rdev->config.evergreen.max_gprs = 256;
3232 rdev->config.evergreen.max_threads = 192;
3233 rdev->config.evergreen.max_gs_threads = 16;
3234 rdev->config.evergreen.max_stack_entries = 256;
3235 rdev->config.evergreen.sx_num_of_sets = 4;
3236 rdev->config.evergreen.sx_max_export_size = 128;
3237 rdev->config.evergreen.sx_max_export_pos_size = 32;
3238 rdev->config.evergreen.sx_max_export_smx_size = 96;
3239 rdev->config.evergreen.max_hw_contexts = 4;
3240 rdev->config.evergreen.sq_num_cf_insts = 1;
3242 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
3243 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3244 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3248 rdev->config.evergreen.num_ses = 1;
3249 rdev->config.evergreen.max_pipes = 2;
3250 rdev->config.evergreen.max_tile_pipes = 2;
3251 rdev->config.evergreen.max_simds = 2;
3252 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
3253 rdev->config.evergreen.max_gprs = 256;
3254 rdev->config.evergreen.max_threads = 192;
3255 rdev->config.evergreen.max_gs_threads = 16;
3256 rdev->config.evergreen.max_stack_entries = 256;
3257 rdev->config.evergreen.sx_num_of_sets = 4;
3258 rdev->config.evergreen.sx_max_export_size = 128;
3259 rdev->config.evergreen.sx_max_export_pos_size = 32;
3260 rdev->config.evergreen.sx_max_export_smx_size = 96;
3261 rdev->config.evergreen.max_hw_contexts = 4;
3262 rdev->config.evergreen.sq_num_cf_insts = 1;
3264 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
3265 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3266 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3270 rdev->config.evergreen.num_ses = 1;
3271 rdev->config.evergreen.max_pipes = 4;
3272 rdev->config.evergreen.max_tile_pipes = 4;
3273 if (rdev->pdev->device == 0x9648)
3274 rdev->config.evergreen.max_simds = 3;
3275 else if ((rdev->pdev->device == 0x9647) ||
3276 (rdev->pdev->device == 0x964a))
3277 rdev->config.evergreen.max_simds = 4;
3279 rdev->config.evergreen.max_simds = 5;
3280 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
3281 rdev->config.evergreen.max_gprs = 256;
3282 rdev->config.evergreen.max_threads = 248;
3283 rdev->config.evergreen.max_gs_threads = 32;
3284 rdev->config.evergreen.max_stack_entries = 256;
3285 rdev->config.evergreen.sx_num_of_sets = 4;
3286 rdev->config.evergreen.sx_max_export_size = 256;
3287 rdev->config.evergreen.sx_max_export_pos_size = 64;
3288 rdev->config.evergreen.sx_max_export_smx_size = 192;
3289 rdev->config.evergreen.max_hw_contexts = 8;
3290 rdev->config.evergreen.sq_num_cf_insts = 2;
3292 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
3293 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3294 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3298 rdev->config.evergreen.num_ses = 1;
3299 rdev->config.evergreen.max_pipes = 4;
3300 rdev->config.evergreen.max_tile_pipes = 4;
3301 rdev->config.evergreen.max_simds = 2;
3302 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
3303 rdev->config.evergreen.max_gprs = 256;
3304 rdev->config.evergreen.max_threads = 248;
3305 rdev->config.evergreen.max_gs_threads = 32;
3306 rdev->config.evergreen.max_stack_entries = 512;
3307 rdev->config.evergreen.sx_num_of_sets = 4;
3308 rdev->config.evergreen.sx_max_export_size = 256;
3309 rdev->config.evergreen.sx_max_export_pos_size = 64;
3310 rdev->config.evergreen.sx_max_export_smx_size = 192;
3311 rdev->config.evergreen.max_hw_contexts = 4;
3312 rdev->config.evergreen.sq_num_cf_insts = 2;
3314 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
3315 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3316 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3320 rdev->config.evergreen.num_ses = 2;
3321 rdev->config.evergreen.max_pipes = 4;
3322 rdev->config.evergreen.max_tile_pipes = 8;
3323 rdev->config.evergreen.max_simds = 7;
3324 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
3325 rdev->config.evergreen.max_gprs = 256;
3326 rdev->config.evergreen.max_threads = 248;
3327 rdev->config.evergreen.max_gs_threads = 32;
3328 rdev->config.evergreen.max_stack_entries = 512;
3329 rdev->config.evergreen.sx_num_of_sets = 4;
3330 rdev->config.evergreen.sx_max_export_size = 256;
3331 rdev->config.evergreen.sx_max_export_pos_size = 64;
3332 rdev->config.evergreen.sx_max_export_smx_size = 192;
3333 rdev->config.evergreen.max_hw_contexts = 8;
3334 rdev->config.evergreen.sq_num_cf_insts = 2;
3336 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
3337 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3338 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3342 rdev->config.evergreen.num_ses = 1;
3343 rdev->config.evergreen.max_pipes = 4;
3344 rdev->config.evergreen.max_tile_pipes = 4;
3345 rdev->config.evergreen.max_simds = 6;
3346 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
3347 rdev->config.evergreen.max_gprs = 256;
3348 rdev->config.evergreen.max_threads = 248;
3349 rdev->config.evergreen.max_gs_threads = 32;
3350 rdev->config.evergreen.max_stack_entries = 256;
3351 rdev->config.evergreen.sx_num_of_sets = 4;
3352 rdev->config.evergreen.sx_max_export_size = 256;
3353 rdev->config.evergreen.sx_max_export_pos_size = 64;
3354 rdev->config.evergreen.sx_max_export_smx_size = 192;
3355 rdev->config.evergreen.max_hw_contexts = 8;
3356 rdev->config.evergreen.sq_num_cf_insts = 2;
3358 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
3359 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3360 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3364 rdev->config.evergreen.num_ses = 1;
3365 rdev->config.evergreen.max_pipes = 2;
3366 rdev->config.evergreen.max_tile_pipes = 2;
3367 rdev->config.evergreen.max_simds = 2;
3368 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
3369 rdev->config.evergreen.max_gprs = 256;
3370 rdev->config.evergreen.max_threads = 192;
3371 rdev->config.evergreen.max_gs_threads = 16;
3372 rdev->config.evergreen.max_stack_entries = 256;
3373 rdev->config.evergreen.sx_num_of_sets = 4;
3374 rdev->config.evergreen.sx_max_export_size = 128;
3375 rdev->config.evergreen.sx_max_export_pos_size = 32;
3376 rdev->config.evergreen.sx_max_export_smx_size = 96;
3377 rdev->config.evergreen.max_hw_contexts = 4;
3378 rdev->config.evergreen.sq_num_cf_insts = 1;
3380 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
3381 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3382 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3400 evergreen_fix_pci_max_read_req_size(rdev);
3403 if ((rdev->family == CHIP_PALM) ||
3404 (rdev->family == CHIP_SUMO) ||
3405 (rdev->family == CHIP_SUMO2))
3417 rdev->config.evergreen.tile_config = 0;
3418 switch (rdev->config.evergreen.max_tile_pipes) {
3421 rdev->config.evergreen.tile_config |= (0 << 0);
3424 rdev->config.evergreen.tile_config |= (1 << 0);
3427 rdev->config.evergreen.tile_config |= (2 << 0);
3430 rdev->config.evergreen.tile_config |= (3 << 0);
3434 if (rdev->flags & RADEON_IS_IGP)
3435 rdev->config.evergreen.tile_config |= 1 << 4;
3439 rdev->config.evergreen.tile_config |= 0 << 4;
3442 rdev->config.evergreen.tile_config |= 1 << 4;
3446 rdev->config.evergreen.tile_config |= 2 << 4;
3450 rdev->config.evergreen.tile_config |= 0 << 8;
3451 rdev->config.evergreen.tile_config |=
3454 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
3464 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {
3477 for (i = 0; i < rdev->config.evergreen.max_backends; i++)
3481 for (i = 0; i < rdev->config.evergreen.max_backends; i++)
3485 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
3491 simd_disable_bitmap |= 0xffffffff << rdev->config.evergreen.max_simds;
3495 rdev->config.evergreen.active_simds = hweight32(~tmp);
3508 if ((rdev->config.evergreen.max_backends == 1) &&
3509 (rdev->flags & RADEON_IS_IGP)) {
3519 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
3522 rdev->config.evergreen.backend_map = tmp;
3548 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
3551 if (rdev->family <= CHIP_SUMO2)
3554 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
3555 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
3556 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
3558 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
3559 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
3560 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
3567 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
3584 switch (rdev->family) {
3599 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
3600 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
3602 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
3603 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
3604 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
3605 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
3607 switch (rdev->family) {
3620 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
3621 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
3622 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
3623 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
3624 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
3626 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
3627 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
3628 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
3629 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
3630 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
3631 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
3648 switch (rdev->family) {
3712 int evergreen_mc_init(struct radeon_device *rdev)
3718 rdev->mc.vram_is_ddr = true;
3719 if ((rdev->family == CHIP_PALM) ||
3720 (rdev->family == CHIP_SUMO) ||
3721 (rdev->family == CHIP_SUMO2))
3748 rdev->mc.vram_width = numchan * chansize;
3750 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
3751 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3753 if ((rdev->family == CHIP_PALM) ||
3754 (rdev->family == CHIP_SUMO) ||
3755 (rdev->family == CHIP_SUMO2)) {
3757 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
3758 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
3761 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
3762 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
3764 rdev->mc.visible_vram_size = rdev->mc.aper_size;
3765 r700_vram_gtt_location(rdev, &rdev->mc);
3766 radeon_update_bandwidth_info(rdev);
3771 void evergreen_print_gpu_status_regs(struct radeon_device *rdev)
3773 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
3775 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
3777 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
3779 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
3781 dev_info(rdev->dev, " SRBM_STATUS2 = 0x%08X\n",
3783 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
3785 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
3787 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
3789 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
3791 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
3793 if (rdev->family >= CHIP_CAYMAN) {
3794 dev_info(rdev->dev, " R_00D834_DMA_STATUS_REG = 0x%08X\n",
3799 bool evergreen_is_display_hung(struct radeon_device *rdev)
3805 for (i = 0; i < rdev->num_crtc; i++) {
3813 for (i = 0; i < rdev->num_crtc; i++) {
3828 u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev)
3880 if (evergreen_is_display_hung(rdev))
3897 static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
3906 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
3908 evergreen_print_gpu_status_regs(rdev);
3922 evergreen_mc_stop(rdev, &save);
3923 if (evergreen_mc_wait_for_idle(rdev)) {
3924 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3969 if (!(rdev->flags & RADEON_IS_IGP)) {
3977 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3991 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4005 evergreen_mc_resume(rdev, &save);
4008 evergreen_print_gpu_status_regs(rdev);
4011 void evergreen_gpu_pci_config_reset(struct radeon_device *rdev)
4016 dev_info(rdev->dev, "GPU pci config reset\n");
4030 r600_rlc_stop(rdev);
4035 rv770_set_clk_bypass_mode(rdev);
4037 pci_clear_master(rdev->pdev);
4039 evergreen_mc_stop(rdev, &save);
4040 if (evergreen_mc_wait_for_idle(rdev)) {
4041 dev_warn(rdev->dev, "Wait for MC idle timed out !\n");
4044 radeon_pci_config_reset(rdev);
4046 for (i = 0; i < rdev->usec_timeout; i++) {
4053 int evergreen_asic_reset(struct radeon_device *rdev, bool hard)
4058 evergreen_gpu_pci_config_reset(rdev);
4062 reset_mask = evergreen_gpu_check_soft_reset(rdev);
4065 r600_set_bios_scratch_engine_hung(rdev, true);
4068 evergreen_gpu_soft_reset(rdev, reset_mask);
4070 reset_mask = evergreen_gpu_check_soft_reset(rdev);
4074 evergreen_gpu_pci_config_reset(rdev);
4076 reset_mask = evergreen_gpu_check_soft_reset(rdev);
4079 r600_set_bios_scratch_engine_hung(rdev, false);
4087 * @rdev: radeon_device pointer
4093 bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
4095 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
4100 radeon_ring_lockup_update(rdev, ring);
4103 return radeon_ring_test_lockup(rdev, ring);
4112 void sumo_rlc_fini(struct radeon_device *rdev)
4117 if (rdev->rlc.save_restore_obj) {
4118 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
4120 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
4121 radeon_bo_unpin(rdev->rlc.save_restore_obj);
4122 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
4124 radeon_bo_unref(&rdev->rlc.save_restore_obj);
4125 rdev->rlc.save_restore_obj = NULL;
4129 if (rdev->rlc.clear_state_obj) {
4130 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
4132 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);
4133 radeon_bo_unpin(rdev->rlc.clear_state_obj);
4134 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
4136 radeon_bo_unref(&rdev->rlc.clear_state_obj);
4137 rdev->rlc.clear_state_obj = NULL;
4141 if (rdev->rlc.cp_table_obj) {
4142 r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false);
4144 dev_warn(rdev->dev, "(%d) reserve RLC cp table bo failed\n", r);
4145 radeon_bo_unpin(rdev->rlc.cp_table_obj);
4146 radeon_bo_unreserve(rdev->rlc.cp_table_obj);
4148 radeon_bo_unref(&rdev->rlc.cp_table_obj);
4149 rdev->rlc.cp_table_obj = NULL;
4155 int sumo_rlc_init(struct radeon_device *rdev)
4165 src_ptr = rdev->rlc.reg_list;
4166 dws = rdev->rlc.reg_list_size;
4167 if (rdev->family >= CHIP_BONAIRE) {
4170 cs_data = rdev->rlc.cs_data;
4174 if (rdev->rlc.save_restore_obj == NULL) {
4175 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
4177 NULL, &rdev->rlc.save_restore_obj);
4179 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
4184 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
4186 sumo_rlc_fini(rdev);
4189 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
4190 &rdev->rlc.save_restore_gpu_addr);
4192 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
4193 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
4194 sumo_rlc_fini(rdev);
4198 r = radeon_bo_kmap(rdev->rlc.save_restore_obj, (void **)&rdev->rlc.sr_ptr);
4200 dev_warn(rdev->dev, "(%d) map RLC sr bo failed\n", r);
4201 sumo_rlc_fini(rdev);
4205 dst_ptr = rdev->rlc.sr_ptr;
4206 if (rdev->family >= CHIP_TAHITI) {
4208 for (i = 0; i < rdev->rlc.reg_list_size; i++)
4228 radeon_bo_kunmap(rdev->rlc.save_restore_obj);
4229 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
4234 if (rdev->family >= CHIP_BONAIRE) {
4235 rdev->rlc.clear_state_size = dws = cik_get_csb_size(rdev);
4236 } else if (rdev->family >= CHIP_TAHITI) {
4237 rdev->rlc.clear_state_size = si_get_csb_size(rdev);
4238 dws = rdev->rlc.clear_state_size + (256 / 4);
4250 rdev->rlc.clear_state_size = dws;
4253 if (rdev->rlc.clear_state_obj == NULL) {
4254 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
4256 NULL, &rdev->rlc.clear_state_obj);
4258 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
4259 sumo_rlc_fini(rdev);
4263 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
4265 sumo_rlc_fini(rdev);
4268 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
4269 &rdev->rlc.clear_state_gpu_addr);
4271 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
4272 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
4273 sumo_rlc_fini(rdev);
4277 r = radeon_bo_kmap(rdev->rlc.clear_state_obj, (void **)&rdev->rlc.cs_ptr);
4279 dev_warn(rdev->dev, "(%d) map RLC c bo failed\n", r);
4280 sumo_rlc_fini(rdev);
4284 dst_ptr = rdev->rlc.cs_ptr;
4285 if (rdev->family >= CHIP_BONAIRE) {
4286 cik_get_csb_buffer(rdev, dst_ptr);
4287 } else if (rdev->family >= CHIP_TAHITI) {
4288 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256;
4291 dst_ptr[2] = cpu_to_le32(rdev->rlc.clear_state_size);
4292 si_get_csb_buffer(rdev, &dst_ptr[(256/4)]);
4295 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4);
4324 radeon_bo_kunmap(rdev->rlc.clear_state_obj);
4325 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
4328 if (rdev->rlc.cp_table_size) {
4329 if (rdev->rlc.cp_table_obj == NULL) {
4330 r = radeon_bo_create(rdev, rdev->rlc.cp_table_size,
4333 NULL, &rdev->rlc.cp_table_obj);
4335 dev_warn(rdev->dev, "(%d) create RLC cp table bo failed\n", r);
4336 sumo_rlc_fini(rdev);
4341 r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false);
4343 dev_warn(rdev->dev, "(%d) reserve RLC cp table bo failed\n", r);
4344 sumo_rlc_fini(rdev);
4347 r = radeon_bo_pin(rdev->rlc.cp_table_obj, RADEON_GEM_DOMAIN_VRAM,
4348 &rdev->rlc.cp_table_gpu_addr);
4350 radeon_bo_unreserve(rdev->rlc.cp_table_obj);
4351 dev_warn(rdev->dev, "(%d) pin RLC cp_table bo failed\n", r);
4352 sumo_rlc_fini(rdev);
4355 r = radeon_bo_kmap(rdev->rlc.cp_table_obj, (void **)&rdev->rlc.cp_table_ptr);
4357 dev_warn(rdev->dev, "(%d) map RLC cp table bo failed\n", r);
4358 sumo_rlc_fini(rdev);
4362 cik_init_cp_pg_table(rdev);
4364 radeon_bo_kunmap(rdev->rlc.cp_table_obj);
4365 radeon_bo_unreserve(rdev->rlc.cp_table_obj);
4372 static void evergreen_rlc_start(struct radeon_device *rdev)
4376 if (rdev->flags & RADEON_IS_IGP) {
4383 int evergreen_rlc_resume(struct radeon_device *rdev)
4388 if (!rdev->rlc_fw)
4391 r600_rlc_stop(rdev);
4395 if (rdev->flags & RADEON_IS_IGP) {
4396 if (rdev->family == CHIP_ARUBA) {
4398 3 | (3 << (16 * rdev->config.cayman.max_shader_engines));
4401 tmp |= 0xffffffff << rdev->config.cayman.max_simds_per_se;
4403 if (tmp == rdev->config.cayman.max_simds_per_se) {
4414 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
4415 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
4426 fw_data = (const __be32 *)rdev->rlc_fw->data;
4427 if (rdev->family >= CHIP_ARUBA) {
4432 } else if (rdev->family >= CHIP_CAYMAN) {
4445 evergreen_rlc_start(rdev);
4452 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
4454 if (crtc >= rdev->num_crtc)
4460 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
4465 if (rdev->family >= CHIP_CAYMAN) {
4466 cayman_cp_int_cntl_setup(rdev, 0,
4468 cayman_cp_int_cntl_setup(rdev, 1, 0);
4469 cayman_cp_int_cntl_setup(rdev, 2, 0);
4478 for (i = 0; i < rdev->num_crtc; i++)
4480 for (i = 0; i < rdev->num_crtc; i++)
4484 if (!ASIC_IS_DCE5(rdev))
4493 int evergreen_irq_set(struct radeon_device *rdev)
4502 if (!rdev->irq.installed) {
4507 if (!rdev->ih.enabled) {
4508 r600_disable_interrupts(rdev);
4510 evergreen_disable_interrupt_state(rdev);
4514 if (rdev->family == CHIP_ARUBA)
4523 if (rdev->family >= CHIP_CAYMAN) {
4525 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
4529 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
4533 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
4538 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
4545 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
4550 if (rdev->family >= CHIP_CAYMAN) {
4552 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
4558 if (rdev->irq.dpm_thermal) {
4563 if (rdev->family >= CHIP_CAYMAN) {
4564 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
4565 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
4566 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
4572 if (rdev->family >= CHIP_CAYMAN)
4577 for (i = 0; i < rdev->num_crtc; i++) {
4579 rdev, INT_MASK + crtc_offsets[i],
4581 rdev->irq.crtc_vblank_int[i] ||
4582 atomic_read(&rdev->irq.pflip[i]), "vblank", i);
4585 for (i = 0; i < rdev->num_crtc; i++)
4590 rdev, DC_HPDx_INT_CONTROL(i),
4592 rdev->irq.hpd[i], "HPD", i);
4595 if (rdev->family == CHIP_ARUBA)
4602 rdev, AFMT_AUDIO_PACKET_CONTROL + crtc_offsets[i],
4604 rdev->irq.afmt[i], "HDMI", i);
4614 static void evergreen_irq_ack(struct radeon_device *rdev)
4617 u32 *grph_int = rdev->irq.stat_regs.evergreen.grph_int;
4618 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;
4619 u32 *afmt_status = rdev->irq.stat_regs.evergreen.afmt_status;
4624 if (i < rdev->num_crtc)
4629 for (i = 0; i < rdev->num_crtc; i += 2) {
4663 static void evergreen_irq_disable(struct radeon_device *rdev)
4665 r600_disable_interrupts(rdev);
4668 evergreen_irq_ack(rdev);
4669 evergreen_disable_interrupt_state(rdev);
4672 void evergreen_irq_suspend(struct radeon_device *rdev)
4674 evergreen_irq_disable(rdev);
4675 r600_rlc_stop(rdev);
4678 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
4682 if (rdev->wb.enabled)
4683 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
4693 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
4694 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
4695 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
4700 return (wptr & rdev->ih.ptr_mask);
4703 int evergreen_irq_process(struct radeon_device *rdev)
4705 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;
4706 u32 *afmt_status = rdev->irq.stat_regs.evergreen.afmt_status;
4720 if (!rdev->ih.enabled || rdev->shutdown)
4723 wptr = evergreen_get_ih_wptr(rdev);
4727 if (atomic_xchg(&rdev->ih.lock, 1))
4730 rptr = rdev->ih.rptr;
4737 evergreen_irq_ack(rdev);
4742 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
4743 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
4758 if (rdev->irq.crtc_vblank_int[crtc_idx]) {
4759 drm_handle_vblank(rdev->ddev, crtc_idx);
4760 rdev->pm.vblank_sync = true;
4761 wake_up(&rdev->irq.vblank_queue);
4763 if (atomic_read(&rdev->irq.pflip[crtc_idx])) {
4764 radeon_crtc_handle_vblank(rdev,
4794 radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
4843 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
4853 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
4854 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
4856 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
4858 cayman_vm_decode_fault(rdev, status, addr);
4864 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4868 if (rdev->family >= CHIP_CAYMAN) {
4871 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4874 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4877 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4881 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4885 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4889 rdev->pm.dpm.thermal.high_to_low = false;
4894 rdev->pm.dpm.thermal.high_to_low = true;
4901 if (rdev->family >= CHIP_CAYMAN) {
4903 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
4913 rptr &= rdev->ih.ptr_mask;
4917 schedule_work(&rdev->dp_work);
4919 schedule_delayed_work(&rdev->hotplug_work, 0);
4921 schedule_work(&rdev->audio_work);
4922 if (queue_thermal && rdev->pm.dpm_enabled)
4923 schedule_work(&rdev->pm.dpm.thermal.work);
4924 rdev->ih.rptr = rptr;
4925 atomic_set(&rdev->ih.lock, 0);
4928 wptr = evergreen_get_ih_wptr(rdev);
4935 static void evergreen_uvd_init(struct radeon_device *rdev)
4939 if (!rdev->has_uvd)
4942 r = radeon_uvd_init(rdev);
4944 dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
4946 * At this point rdev->uvd.vcpu_bo is NULL which trickles down
4951 rdev->has_uvd = false;
4954 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
4955 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
4958 static void evergreen_uvd_start(struct radeon_device *rdev)
4962 if (!rdev->has_uvd)
4965 r = uvd_v2_2_resume(rdev);
4967 dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
4970 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
4972 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
4978 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
4981 static void evergreen_uvd_resume(struct radeon_device *rdev)
4986 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
4989 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
4990 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
4992 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
4995 r = uvd_v1_0_init(rdev);
4997 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
5002 static int evergreen_startup(struct radeon_device *rdev)
5008 evergreen_pcie_gen2_enable(rdev);
5010 evergreen_program_aspm(rdev);
5013 r = r600_vram_scratch_init(rdev);
5017 evergreen_mc_program(rdev);
5019 if (ASIC_IS_DCE5(rdev) && !rdev->pm.dpm_enabled) {
5020 r = ni_mc_load_microcode(rdev);
5027 if (rdev->flags & RADEON_IS_AGP) {
5028 evergreen_agp_enable(rdev);
5030 r = evergreen_pcie_gart_enable(rdev);
5034 evergreen_gpu_init(rdev);
5037 if (rdev->flags & RADEON_IS_IGP) {
5038 rdev->rlc.reg_list = sumo_rlc_save_restore_register_list;
5039 rdev->rlc.reg_list_size =
5041 rdev->rlc.cs_data = evergreen_cs_data;
5042 r = sumo_rlc_init(rdev);
5050 r = radeon_wb_init(rdev);
5054 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
5056 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
5060 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
5062 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
5066 evergreen_uvd_start(rdev);
5069 if (!rdev->irq.installed) {
5070 r = radeon_irq_kms_init(rdev);
5075 r = r600_irq_init(rdev);
5078 radeon_irq_kms_fini(rdev);
5081 evergreen_irq_set(rdev);
5083 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
5084 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
5089 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
5090 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
5095 r = evergreen_cp_load_microcode(rdev);
5098 r = evergreen_cp_resume(rdev);
5101 r = r600_dma_resume(rdev);
5105 evergreen_uvd_resume(rdev);
5107 r = radeon_ib_pool_init(rdev);
5109 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
5113 r = radeon_audio_init(rdev);
5122 int evergreen_resume(struct radeon_device *rdev)
5129 if (radeon_asic_reset(rdev))
5130 dev_warn(rdev->dev, "GPU reset failed !\n");
5136 atom_asic_init(rdev->mode_info.atom_context);
5139 evergreen_init_golden_registers(rdev);
5141 if (rdev->pm.pm_method == PM_METHOD_DPM)
5142 radeon_pm_resume(rdev);
5144 rdev->accel_working = true;
5145 r = evergreen_startup(rdev);
5148 rdev->accel_working = false;
5156 int evergreen_suspend(struct radeon_device *rdev)
5158 radeon_pm_suspend(rdev);
5159 radeon_audio_fini(rdev);
5160 if (rdev->has_uvd) {
5161 radeon_uvd_suspend(rdev);
5162 uvd_v1_0_fini(rdev);
5164 r700_cp_stop(rdev);
5165 r600_dma_stop(rdev);
5166 evergreen_irq_suspend(rdev);
5167 radeon_wb_disable(rdev);
5168 evergreen_pcie_gart_disable(rdev);
5179 int evergreen_init(struct radeon_device *rdev)
5184 if (!radeon_get_bios(rdev)) {
5185 if (ASIC_IS_AVIVO(rdev))
5189 if (!rdev->is_atom_bios) {
5190 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
5193 r = radeon_atombios_init(rdev);
5199 if (radeon_asic_reset(rdev))
5200 dev_warn(rdev->dev, "GPU reset failed !\n");
5202 if (!radeon_card_posted(rdev)) {
5203 if (!rdev->bios) {
5204 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
5208 atom_asic_init(rdev->mode_info.atom_context);
5211 evergreen_init_golden_registers(rdev);
5213 r600_scratch_init(rdev);
5215 radeon_surface_init(rdev);
5217 radeon_get_clock_info(rdev->ddev);
5219 radeon_fence_driver_init(rdev);
5221 if (rdev->flags & RADEON_IS_AGP) {
5222 r = radeon_agp_init(rdev);
5224 radeon_agp_disable(rdev);
5227 r = evergreen_mc_init(rdev);
5231 r = radeon_bo_init(rdev);
5235 if (ASIC_IS_DCE5(rdev)) {
5236 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
5237 r = ni_init_microcode(rdev);
5244 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
5245 r = r600_init_microcode(rdev);
5254 radeon_pm_init(rdev);
5256 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
5257 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
5259 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
5260 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
5262 evergreen_uvd_init(rdev);
5264 rdev->ih.ring_obj = NULL;
5265 r600_ih_ring_init(rdev, 64 * 1024);
5267 r = r600_pcie_gart_init(rdev);
5271 rdev->accel_working = true;
5272 r = evergreen_startup(rdev);
5274 dev_err(rdev->dev, "disabling GPU acceleration\n");
5275 r700_cp_fini(rdev);
5276 r600_dma_fini(rdev);
5277 r600_irq_fini(rdev);
5278 if (rdev->flags & RADEON_IS_IGP)
5279 sumo_rlc_fini(rdev);
5280 radeon_wb_fini(rdev);
5281 radeon_ib_pool_fini(rdev);
5282 radeon_irq_kms_fini(rdev);
5283 evergreen_pcie_gart_fini(rdev);
5284 rdev->accel_working = false;
5291 if (ASIC_IS_DCE5(rdev)) {
5292 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
5301 void evergreen_fini(struct radeon_device *rdev)
5303 radeon_pm_fini(rdev);
5304 radeon_audio_fini(rdev);
5305 r700_cp_fini(rdev);
5306 r600_dma_fini(rdev);
5307 r600_irq_fini(rdev);
5308 if (rdev->flags & RADEON_IS_IGP)
5309 sumo_rlc_fini(rdev);
5310 radeon_wb_fini(rdev);
5311 radeon_ib_pool_fini(rdev);
5312 radeon_irq_kms_fini(rdev);
5313 uvd_v1_0_fini(rdev);
5314 radeon_uvd_fini(rdev);
5315 evergreen_pcie_gart_fini(rdev);
5316 r600_vram_scratch_fini(rdev);
5317 radeon_gem_fini(rdev);
5318 radeon_fence_driver_fini(rdev);
5319 radeon_agp_fini(rdev);
5320 radeon_bo_fini(rdev);
5321 radeon_atombios_fini(rdev);
5322 kfree(rdev->bios);
5323 rdev->bios = NULL;
5326 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
5333 if (rdev->flags & RADEON_IS_IGP)
5336 if (!(rdev->flags & RADEON_IS_PCIE))
5340 if (ASIC_IS_X2(rdev))
5343 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
5344 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
5389 void evergreen_program_aspm(struct radeon_device *rdev)
5404 if (!(rdev->flags & RADEON_IS_PCIE))
5407 switch (rdev->family) {
5424 if (rdev->flags & RADEON_IS_IGP)
5446 if (rdev->family >= CHIP_BARTS)
5453 if (rdev->family >= CHIP_BARTS)
5483 if (rdev->family >= CHIP_BARTS) {
5515 if (rdev->family >= CHIP_BARTS) {
5532 if (rdev->family < CHIP_BARTS)