Lines Matching defs:mode
1199 /* put PLL in bypass mode */
1203 /* keep the Bypass mode, put PLL to sleep */
1260 /* switch from bypass mode to normal mode */
1505 * Initialize the power states used in profile mode
1507 * Used for profile mode only.
1565 * Initialize the power states used in profile mode
1567 * Used for profile mode only.
1827 struct drm_display_mode *mode,
1853 if (radeon_crtc->base.enabled && mode) {
1882 if (radeon_crtc->base.enabled && mode) {
1941 bool interlaced; /* mode is interlaced */
2041 /* Calculate the display mode Average Bandwidth
2158 struct drm_display_mode *mode = &radeon_crtc->base.mode;
2171 if (radeon_crtc->base.enabled && num_heads && mode) {
2172 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
2173 (u32)mode->clock);
2174 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
2175 (u32)mode->clock);
2192 wm_high.disp_clk = mode->clock;
2193 wm_high.src_width = mode->crtc_hdisplay;
2197 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2219 wm_low.disp_clk = mode->clock;
2220 wm_low.src_width = mode->crtc_hdisplay;
2224 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2241 /* should really do this at mode validation time... */
2258 b.full = dfixed_const(mode->clock);
2270 b.full = dfixed_const(mode->clock);
2282 radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
2320 * Update the display watermarks based on the requested mode(s)
2340 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
2341 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
2562 * insure that it enable and in DP_SST mode.
2601 /* if dig_be in sst mode? */
2623 * Blank dig when in dp sst mode
2937 /* set to DX10/11 mode */