Lines Matching refs:mclk
422 u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
429 if (mclk <= pi->mclk_strobe_mode_threshold)
431 result = cypress_get_mclk_frequency_ratio(rdev, mclk, strobe_mode);
474 RV7XX_SMC_MCLK_VALUE *mclk,
600 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock);
601 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
602 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
603 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
604 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
605 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
606 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
607 mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1);
608 mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2);
655 u32 mclk,
667 if (mclk <= pi->mvdd_split_frequency) {
700 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
710 if (pl->mclk > pi->mclk_edc_enable_threshold)
713 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
716 level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk);
719 if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >=
729 pl->mclk,
730 &level->mclk,
736 pl->mclk,
737 &level->mclk,
760 ret = cypress_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
838 if (pl->mclk <=
937 new_state->low.mclk));
940 new_state->medium.mclk));
943 new_state->high.mclk));
1053 range_table->mclk[i];
1054 radeon_atom_set_ac_timing(rdev, range_table->mclk[i]);
1130 radeon_atom_set_ac_timing(rdev, boot_state->low.mclk);
1149 boot_state->low.mclk);
1207 boot_state->low.mclk);
1246 table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
1248 table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
1250 table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
1252 table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
1254 table->initialState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
1256 table->initialState.levels[0].mclk.mclk770.vDLL_CNTL =
1259 table->initialState.levels[0].mclk.mclk770.vMPLL_SS =
1261 table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 =
1264 table->initialState.levels[0].mclk.mclk770.mclk_value =
1265 cpu_to_be32(initial_state->low.mclk);
1317 initial_state->low.mclk);
1319 if (initial_state->low.mclk > pi->mclk_edc_enable_threshold)
1436 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
1438 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
1440 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
1442 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
1444 table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
1446 table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
1448 table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0;