Lines Matching defs:rdev
48 static void cypress_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
51 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
85 static void cypress_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
88 cypress_enable_bif_dynamic_pcie_gen2(rdev, enable);
97 static int cypress_enter_ulp_state(struct radeon_device *rdev)
99 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
118 static void cypress_gfx_clock_gating_enable(struct radeon_device *rdev,
121 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
170 static void cypress_mg_clock_gating_enable(struct radeon_device *rdev,
173 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
174 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
179 if (rdev->family == CHIP_CEDAR)
181 else if (rdev->family == CHIP_REDWOOD)
219 void cypress_enable_spread_spectrum(struct radeon_device *rdev,
222 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
238 void cypress_start_dpm(struct radeon_device *rdev)
243 void cypress_enable_sclk_control(struct radeon_device *rdev,
252 void cypress_enable_mclk_control(struct radeon_device *rdev,
261 int cypress_notify_smc_display_change(struct radeon_device *rdev,
267 if (rv770_send_msg_to_smc(rdev, msg) != PPSMC_Result_OK)
273 void cypress_program_response_times(struct radeon_device *rdev)
278 reference_clock = radeon_get_xclk(rdev);
281 rv770_write_smc_soft_register(rdev,
285 rv770_write_smc_soft_register(rdev,
288 rv770_write_smc_soft_register(rdev,
291 rv770_program_response_times(rdev);
293 if (ASIC_IS_LOMBOK(rdev))
294 rv770_write_smc_soft_register(rdev,
299 static int cypress_pcie_performance_request(struct radeon_device *rdev,
303 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
316 return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
320 return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
327 void cypress_advertise_gen2_capability(struct radeon_device *rdev)
329 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
333 radeon_acpi_pcie_notify_device_ready(rdev);
345 cypress_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, true);
358 void cypress_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
376 cypress_pcie_performance_request(rdev, request, false);
380 void cypress_notify_link_speed_change_before_state_change(struct radeon_device *rdev,
398 cypress_pcie_performance_request(rdev, request, false);
402 static int cypress_populate_voltage_value(struct radeon_device *rdev,
422 u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
424 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
431 result = cypress_get_mclk_frequency_ratio(rdev, mclk, strobe_mode);
440 u32 cypress_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf)
442 u32 ref_clk = rdev->clock.mpll.reference_freq;
472 static int cypress_populate_mclk_value(struct radeon_device *rdev,
477 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
499 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
511 ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);
556 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
558 u32 reference_clock = rdev->clock.mpll.reference_freq;
613 u8 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev,
618 if (rdev->family >= CHIP_BARTS) {
654 static int cypress_populate_mvdd_value(struct radeon_device *rdev,
658 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
659 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
678 int cypress_convert_power_level_to_smc(struct radeon_device *rdev,
683 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
684 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
694 ret = rv740_populate_sclk_value(rdev, pl->sclk, &level->sclk);
716 level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk);
719 if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >=
727 ret = cypress_populate_mclk_value(rdev,
734 ret = cypress_populate_mclk_value(rdev,
744 ret = cypress_populate_voltage_value(rdev,
752 ret = cypress_populate_voltage_value(rdev,
760 ret = cypress_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
765 static int cypress_convert_power_state_to_smc(struct radeon_device *rdev,
770 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
776 ret = cypress_convert_power_level_to_smc(rdev,
783 ret = cypress_convert_power_level_to_smc(rdev,
790 ret = cypress_convert_power_level_to_smc(rdev,
811 rv770_populate_smc_sp(rdev, radeon_state, smc_state);
813 return rv770_populate_smc_t(rdev, radeon_state, smc_state);
830 static void cypress_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
834 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
852 static void cypress_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
858 cypress_convert_mc_reg_table_entry_to_smc(rdev,
861 cypress_convert_mc_reg_table_entry_to_smc(rdev,
864 cypress_convert_mc_reg_table_entry_to_smc(rdev,
869 int cypress_upload_sw_state(struct radeon_device *rdev,
872 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
878 ret = cypress_convert_power_state_to_smc(rdev, radeon_new_state, &state);
882 return rv770_copy_bytes_to_smc(rdev, address, (u8 *)&state,
887 int cypress_upload_mc_reg_table(struct radeon_device *rdev,
890 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
891 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
895 cypress_convert_mc_reg_table_to_smc(rdev, radeon_new_state, &mc_reg_table);
900 return rv770_copy_bytes_to_smc(rdev, address,
906 u32 cypress_calculate_burst_time(struct radeon_device *rdev,
909 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
927 void cypress_program_memory_timing_parameters(struct radeon_device *rdev,
935 mc_arb_burst_time |= STATE1(cypress_calculate_burst_time(rdev,
938 mc_arb_burst_time |= STATE2(cypress_calculate_burst_time(rdev,
941 mc_arb_burst_time |= STATE3(cypress_calculate_burst_time(rdev,
945 rv730_program_memory_timing_parameters(rdev, radeon_new_state);
950 static void cypress_populate_mc_reg_addresses(struct radeon_device *rdev,
953 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
969 static void cypress_set_mc_reg_address_table(struct radeon_device *rdev)
971 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1033 static void cypress_retrieve_ac_timing_for_one_entry(struct radeon_device *rdev,
1036 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1045 static void cypress_retrieve_ac_timing_for_all_ranges(struct radeon_device *rdev,
1048 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1054 radeon_atom_set_ac_timing(rdev, range_table->mclk[i]);
1055 cypress_retrieve_ac_timing_for_one_entry(rdev,
1073 static int cypress_initialize_mc_reg_table(struct radeon_device *rdev)
1075 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1076 u8 module_index = rv770_get_memory_module_index(rdev);
1080 ret = radeon_atom_get_mclk_range_table(rdev,
1086 cypress_retrieve_ac_timing_for_all_ranges(rdev, &range_table);
1091 static void cypress_wait_for_mc_sequencer(struct radeon_device *rdev, u8 value)
1096 if ((rdev->family == CHIP_CYPRESS) ||
1097 (rdev->family == CHIP_HEMLOCK))
1099 else if (rdev->family == CHIP_CEDAR)
1103 if ((rdev->family == CHIP_CYPRESS) ||
1104 (rdev->family == CHIP_HEMLOCK)) {
1111 for (j = 0; j < rdev->usec_timeout; j++) {
1119 static void cypress_force_mc_use_s1(struct radeon_device *rdev,
1130 radeon_atom_set_ac_timing(rdev, boot_state->low.mclk);
1131 radeon_mc_wait_for_idle(rdev);
1133 if ((rdev->family == CHIP_CYPRESS) ||
1134 (rdev->family == CHIP_HEMLOCK)) {
1142 for (i = 0; i < rdev->num_crtc; i++)
1143 radeon_wait_for_vblank(rdev, i);
1146 cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_SUSPEND);
1148 strobe_mode = cypress_get_strobe_mode_settings(rdev,
1155 for (i = 0; i < rdev->usec_timeout; i++) {
1165 cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_RESUME);
1168 static void cypress_copy_ac_timing_from_s1_to_s0(struct radeon_device *rdev)
1170 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1180 static void cypress_force_mc_use_s0(struct radeon_device *rdev,
1188 cypress_copy_ac_timing_from_s1_to_s0(rdev);
1189 radeon_mc_wait_for_idle(rdev);
1191 if ((rdev->family == CHIP_CYPRESS) ||
1192 (rdev->family == CHIP_HEMLOCK)) {
1200 for (i = 0; i < rdev->num_crtc; i++)
1201 radeon_wait_for_vblank(rdev, i);
1204 cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_SUSPEND);
1206 strobe_mode = cypress_get_strobe_mode_settings(rdev,
1213 for (i = 0; i < rdev->usec_timeout; i++) {
1223 cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_RESUME);
1226 static int cypress_populate_initial_mvdd_value(struct radeon_device *rdev,
1229 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1237 int cypress_populate_smc_initial_state(struct radeon_device *rdev,
1242 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1243 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1285 cypress_populate_voltage_value(rdev,
1291 cypress_populate_voltage_value(rdev,
1296 cypress_populate_initial_mvdd_value(rdev,
1316 cypress_get_strobe_mode_settings(rdev,
1333 int cypress_populate_smc_acpi_state(struct radeon_device *rdev,
1336 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1337 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1362 cypress_populate_voltage_value(rdev,
1378 cypress_populate_voltage_value(rdev,
1387 cypress_populate_voltage_value(rdev,
1430 if (rdev->family <= CHIP_HEMLOCK)
1459 cypress_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
1470 static void cypress_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
1486 int cypress_construct_voltage_tables(struct radeon_device *rdev)
1488 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1491 ret = radeon_atom_get_voltage_table(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0,
1497 cypress_trim_voltage_table_to_fit_state_table(rdev,
1501 ret = radeon_atom_get_voltage_table(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0,
1507 cypress_trim_voltage_table_to_fit_state_table(rdev,
1514 static void cypress_populate_smc_voltage_table(struct radeon_device *rdev,
1526 int cypress_populate_smc_voltage_tables(struct radeon_device *rdev,
1529 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1530 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1534 cypress_populate_smc_voltage_table(rdev,
1552 cypress_populate_smc_voltage_table(rdev,
1573 int cypress_get_mvdd_configuration(struct radeon_device *rdev)
1575 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1576 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1596 module_index = rv770_get_memory_module_index(rdev);
1598 if (radeon_atom_get_memory_info(rdev, module_index, &memory_info)) {
1614 static int cypress_init_smc_table(struct radeon_device *rdev,
1617 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1623 cypress_populate_smc_voltage_tables(rdev, table);
1625 switch (rdev->pm.int_thermal_type) {
1638 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
1641 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1644 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1650 ret = cypress_populate_smc_initial_state(rdev, radeon_boot_state, table);
1654 ret = cypress_populate_smc_acpi_state(rdev, table);
1660 return rv770_copy_bytes_to_smc(rdev,
1666 int cypress_populate_mc_reg_table(struct radeon_device *rdev,
1669 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1670 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1674 rv770_write_smc_soft_register(rdev,
1677 cypress_populate_mc_reg_addresses(rdev, &mc_reg_table);
1679 cypress_convert_mc_reg_table_entry_to_smc(rdev,
1687 cypress_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, &mc_reg_table);
1689 return rv770_copy_bytes_to_smc(rdev, eg_pi->mc_reg_table_start,
1694 int cypress_get_table_locations(struct radeon_device *rdev)
1696 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1697 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1701 ret = rv770_read_smc_sram_dword(rdev,
1710 ret = rv770_read_smc_sram_dword(rdev,
1719 ret = rv770_read_smc_sram_dword(rdev,
1731 void cypress_enable_display_gap(struct radeon_device *rdev)
1745 static void cypress_program_display_gap(struct radeon_device *rdev)
1751 if (rdev->pm.dpm.new_active_crtc_count > 0)
1756 if (rdev->pm.dpm.new_active_crtc_count > 1)
1766 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
1767 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
1769 for (i = 0; i < rdev->num_crtc; i++) {
1770 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
1773 if (i == rdev->num_crtc)
1783 cypress_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
1786 void cypress_dpm_setup_asic(struct radeon_device *rdev)
1788 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1790 rv740_read_clock_registers(rdev);
1791 rv770_read_voltage_smio_registers(rdev);
1792 rv770_get_max_vddc(rdev);
1793 rv770_get_memory_type(rdev);
1799 cypress_advertise_gen2_capability(rdev);
1801 rv770_get_pcie_gen2_status(rdev);
1803 rv770_enable_acpi_pm(rdev);
1806 int cypress_dpm_enable(struct radeon_device *rdev)
1808 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1809 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1810 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1814 rv770_restore_cgcg(rdev);
1816 if (rv770_dpm_enabled(rdev))
1820 rv770_enable_voltage_control(rdev, true);
1821 ret = cypress_construct_voltage_tables(rdev);
1829 ret = cypress_get_mvdd_configuration(rdev);
1837 cypress_set_mc_reg_address_table(rdev);
1838 cypress_force_mc_use_s0(rdev, boot_ps);
1839 ret = cypress_initialize_mc_reg_table(rdev);
1842 cypress_force_mc_use_s1(rdev, boot_ps);
1845 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1846 rv770_enable_backbias(rdev, true);
1849 cypress_enable_spread_spectrum(rdev, true);
1852 rv770_enable_thermal_protection(rdev, true);
1854 rv770_setup_bsp(rdev);
1855 rv770_program_git(rdev);
1856 rv770_program_tp(rdev);
1857 rv770_program_tpp(rdev);
1858 rv770_program_sstp(rdev);
1859 rv770_program_engine_speed_parameters(rdev);
1860 cypress_enable_display_gap(rdev);
1861 rv770_program_vc(rdev);
1864 cypress_enable_dynamic_pcie_gen2(rdev, true);
1866 ret = rv770_upload_firmware(rdev);
1872 ret = cypress_get_table_locations(rdev);
1877 ret = cypress_init_smc_table(rdev, boot_ps);
1883 ret = cypress_populate_mc_reg_table(rdev, boot_ps);
1890 cypress_program_response_times(rdev);
1892 r7xx_start_smc(rdev);
1894 ret = cypress_notify_smc_display_change(rdev, false);
1899 cypress_enable_sclk_control(rdev, true);
1902 cypress_enable_mclk_control(rdev, true);
1904 cypress_start_dpm(rdev);
1907 cypress_gfx_clock_gating_enable(rdev, true);
1910 cypress_mg_clock_gating_enable(rdev, true);
1912 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
1917 void cypress_dpm_disable(struct radeon_device *rdev)
1919 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1920 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1921 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1923 if (!rv770_dpm_enabled(rdev))
1926 rv770_clear_vc(rdev);
1929 rv770_enable_thermal_protection(rdev, false);
1932 cypress_enable_dynamic_pcie_gen2(rdev, false);
1934 if (rdev->irq.installed &&
1935 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1936 rdev->irq.dpm_thermal = false;
1937 radeon_irq_set(rdev);
1941 cypress_gfx_clock_gating_enable(rdev, false);
1944 cypress_mg_clock_gating_enable(rdev, false);
1946 rv770_stop_dpm(rdev);
1947 r7xx_stop_smc(rdev);
1949 cypress_enable_spread_spectrum(rdev, false);
1952 cypress_force_mc_use_s1(rdev, boot_ps);
1954 rv770_reset_smio_status(rdev);
1957 int cypress_dpm_set_power_state(struct radeon_device *rdev)
1959 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1960 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
1961 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
1964 ret = rv770_restrict_performance_levels_before_switch(rdev);
1970 cypress_notify_link_speed_change_before_state_change(rdev, new_ps, old_ps);
1972 rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
1973 ret = rv770_halt_smc(rdev);
1978 ret = cypress_upload_sw_state(rdev, new_ps);
1984 ret = cypress_upload_mc_reg_table(rdev, new_ps);
1991 cypress_program_memory_timing_parameters(rdev, new_ps);
1993 ret = rv770_resume_smc(rdev);
1998 ret = rv770_set_sw_state(rdev);
2003 rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
2006 cypress_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
2012 void cypress_dpm_reset_asic(struct radeon_device *rdev)
2014 rv770_restrict_performance_levels_before_switch(rdev);
2015 rv770_set_boot_state(rdev);
2019 void cypress_dpm_display_configuration_changed(struct radeon_device *rdev)
2021 cypress_program_display_gap(rdev);
2024 int cypress_dpm_init(struct radeon_device *rdev)
2034 rdev->pm.dpm.priv = eg_pi;
2037 rv770_get_max_vddc(rdev);
2045 ret = r600_get_platform_caps(rdev);
2049 ret = rv7xx_parse_power_table(rdev);
2053 if (rdev->pm.dpm.voltage_response_time == 0)
2054 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
2055 if (rdev->pm.dpm.backbias_response_time == 0)
2056 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
2058 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2075 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0);
2078 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0);
2081 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0);
2083 rv770_get_engine_memory_ss(rdev);
2091 if ((rdev->family == CHIP_CYPRESS) ||
2092 (rdev->family == CHIP_HEMLOCK))
2104 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
2111 if (rdev->flags & RADEON_IS_MOBILITY)
2125 radeon_acpi_is_pcie_performance_request_supported(rdev);
2130 if ((rdev->family == CHIP_CYPRESS) ||
2131 (rdev->family == CHIP_HEMLOCK) ||
2132 (rdev->family == CHIP_JUNIPER))
2145 void cypress_dpm_fini(struct radeon_device *rdev)
2149 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2150 kfree(rdev->pm.dpm.ps[i].ps_priv);
2152 kfree(rdev->pm.dpm.ps);
2153 kfree(rdev->pm.dpm.priv);
2156 bool cypress_dpm_vblank_too_short(struct radeon_device *rdev)
2158 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2159 u32 vblank_time = r600_dpm_get_vblank_time(rdev);