Lines Matching refs:ring
42 * and each one supports 1 ring buffer used for gfx
46 * (ring buffer, IBs, etc.), but sDMA has it's own
58 * @ring: radeon ring pointer
63 struct radeon_ring *ring)
68 rptr = rdev->wb.wb[ring->rptr_offs/4];
70 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
85 * @ring: radeon ring pointer
90 struct radeon_ring *ring)
94 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
106 * @ring: radeon ring pointer
111 struct radeon_ring *ring)
115 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
120 WREG32(reg, (ring->wptr << 2) & 0x3fffc);
130 * Schedule an IB in the DMA ring (CIK).
135 struct radeon_ring *ring = &rdev->ring[ib->ring];
136 u32 extra_bits = (ib->vm ? ib->vm->ids[ib->ring].id : 0) & 0xf;
139 u32 next_rptr = ring->wptr + 5;
143 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
144 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
145 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
146 radeon_ring_write(ring, 1); /* number of DWs to follow */
147 radeon_ring_write(ring, next_rptr);
151 while ((ring->wptr & 7) != 4)
152 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
153 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
154 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
155 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));
156 radeon_ring_write(ring, ib->length_dw);
161 * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
164 * @ridx: radeon ring index
166 * Emit an hdp flush packet on the requested DMA ring.
171 struct radeon_ring *ring = &rdev->ring[ridx];
181 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
182 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE);
183 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ);
184 radeon_ring_write(ring, ref_and_mask); /* reference */
185 radeon_ring_write(ring, ref_and_mask); /* mask */
186 radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
190 * cik_sdma_fence_ring_emit - emit a fence on the DMA ring
195 * Add a DMA fence packet to the ring to write
202 struct radeon_ring *ring = &rdev->ring[fence->ring];
203 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
206 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
207 radeon_ring_write(ring, lower_32_bits(addr));
208 radeon_ring_write(ring, upper_32_bits(addr));
209 radeon_ring_write(ring, fence->seq);
211 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
213 cik_sdma_hdp_flush_ring_emit(rdev, fence->ring);
217 * cik_sdma_semaphore_ring_emit - emit a semaphore on the dma ring
220 * @ring: radeon_ring structure holding ring information
224 * Add a DMA semaphore packet to the ring wait on or signal
228 struct radeon_ring *ring,
235 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));
236 radeon_ring_write(ring, addr & 0xfffffff8);
237 radeon_ring_write(ring, upper_32_bits(addr));
247 * Stop the gfx async dma ring buffers (CIK).
268 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
269 rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;
361 * Set up the gfx DMA ring buffers and enable them (CIK).
366 struct radeon_ring *ring;
374 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
378 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
386 /* Set ring buffer size in dwords */
387 rb_bufsz = order_base_2(ring->ring_size / 4);
394 /* Initialize the ring buffer's read and write pointers */
407 WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8);
408 WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40);
410 ring->wptr = 0;
411 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2);
423 ring->ready = true;
425 r = radeon_ring_test(rdev, ring->idx, ring);
427 ring->ready = false;
560 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
561 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
586 struct radeon_ring *ring = &rdev->ring[ring_index];
595 r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14);
603 radeon_sync_rings(rdev, &sync, ring->idx);
610 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0));
611 radeon_ring_write(ring, cur_size_in_bytes);
612 radeon_ring_write(ring, 0); /* src/dst endian swap */
613 radeon_ring_write(ring, lower_32_bits(src_offset));
614 radeon_ring_write(ring, upper_32_bits(src_offset));
615 radeon_ring_write(ring, lower_32_bits(dst_offset));
616 radeon_ring_write(ring, upper_32_bits(dst_offset));
621 r = radeon_fence_emit(rdev, &fence, ring->idx);
623 radeon_ring_unlock_undo(rdev, ring);
628 radeon_ring_unlock_commit(rdev, ring, false);
638 * @ring: radeon_ring structure holding ring information
645 struct radeon_ring *ring)
653 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
663 r = radeon_ring_lock(rdev, ring, 5);
665 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
668 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
669 radeon_ring_write(ring, lower_32_bits(gpu_addr));
670 radeon_ring_write(ring, upper_32_bits(gpu_addr));
671 radeon_ring_write(ring, 1); /* number of DWs to follow */
672 radeon_ring_write(ring, 0xDEADBEEF);
673 radeon_ring_unlock_commit(rdev, ring, false);
683 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
685 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
686 ring->idx, tmp);
696 * @ring: radeon_ring structure holding ring information
698 * Test a simple IB in the DMA ring (CIK).
701 int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
710 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
720 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
756 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
769 * @ring: radeon_ring structure holding ring information
774 bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
779 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
785 radeon_ring_lockup_update(rdev, ring);
788 return radeon_ring_test_lockup(rdev, ring);
944 void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
950 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
952 radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2);
954 radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2);
956 radeon_ring_write(ring, pd_addr >> 12);
959 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
960 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
961 radeon_ring_write(ring, VMID(vm_id));
963 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
964 radeon_ring_write(ring, SH_MEM_BASES >> 2);
965 radeon_ring_write(ring, 0);
967 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
968 radeon_ring_write(ring, SH_MEM_CONFIG >> 2);
969 radeon_ring_write(ring, 0);
971 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
972 radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2);
973 radeon_ring_write(ring, 1);
975 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
976 radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2);
977 radeon_ring_write(ring, 0);
979 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
980 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
981 radeon_ring_write(ring, VMID(0));
984 cik_sdma_hdp_flush_ring_emit(rdev, ring->idx);
987 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
988 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
989 radeon_ring_write(ring, 1 << vm_id);
991 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
992 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
993 radeon_ring_write(ring, 0);
994 radeon_ring_write(ring, 0); /* reference */
995 radeon_ring_write(ring, 0); /* mask */
996 radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */