Lines Matching refs:macrotile
2323 u32 *macrotile = rdev->config.cik.macrotile_mode_array;
2353 macrotile[reg_offset] = 0;
2436 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2440 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2444 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2448 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2452 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2456 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2460 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2464 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2468 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2472 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2476 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2480 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2484 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2488 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2496 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
2579 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2583 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2587 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2591 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2595 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2599 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2603 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2607 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2611 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2615 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2619 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2623 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2627 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2631 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2639 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
2804 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2808 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2812 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2816 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2820 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2824 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2828 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2832 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2836 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2840 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2844 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2848 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2852 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2856 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2864 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
2947 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2951 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2955 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2959 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2963 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2967 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2971 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2975 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2979 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2983 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2987 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2991 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2995 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2999 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3007 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);