Lines Matching defs:tmp
1864 u32 running, tmp;
1920 tmp = RREG32(MC_SEQ_MISC0);
1921 if ((rdev->pdev->device == 0x6649) && ((tmp & 0xff00) == 0x5600)) {
3173 u32 tmp;
3269 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
3270 rdev->config.cik.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
3354 tmp = RREG32(SPI_CONFIG_CNTL);
3355 tmp |= 0x03000000;
3356 WREG32(SPI_CONFIG_CNTL, tmp);
3362 tmp = RREG32(DB_DEBUG2) & ~0xf00fffff;
3363 tmp |= 0x00000400;
3364 WREG32(DB_DEBUG2, tmp);
3366 tmp = RREG32(DB_DEBUG3) & ~0x0002021c;
3367 tmp |= 0x00020200;
3368 WREG32(DB_DEBUG3, tmp);
3370 tmp = RREG32(CB_HW_CONTROL) & ~0x00010000;
3371 tmp |= 0x00018208;
3372 WREG32(CB_HW_CONTROL, tmp);
3396 tmp = RREG32(HDP_MISC_CNTL);
3397 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
3398 WREG32(HDP_MISC_CNTL, tmp);
3448 uint32_t tmp = 0;
3470 tmp = RREG32(scratch);
3471 if (tmp == 0xDEADBEEF)
3479 ring->idx, scratch, tmp);
3773 uint32_t tmp = 0;
3815 tmp = RREG32(scratch);
3816 if (tmp == 0xDEADBEEF)
3824 scratch, tmp);
4049 u32 tmp;
4070 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
4072 tmp |= BUF_SWAP_32BIT;
4074 WREG32(CP_RB0_CNTL, tmp);
4077 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
4089 tmp |= RB_NO_UPDATE;
4092 WREG32(CP_RB0_CNTL, tmp);
4187 u32 j, tmp;
4191 tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
4192 tmp &= ~WPTR_POLL_EN;
4193 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
4511 u32 tmp;
4525 tmp = RREG32(CP_CPF_DEBUG);
4526 tmp |= (1 << 23);
4527 WREG32(CP_CPF_DEBUG, tmp);
4547 tmp = RREG32(CP_HPD_EOP_CONTROL);
4548 tmp &= ~EOP_SIZE_MASK;
4549 tmp |= order_base_2(MEC_HPD_SIZE / 8);
4550 WREG32(CP_HPD_EOP_CONTROL, tmp);
4610 tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
4611 tmp &= ~WPTR_POLL_EN;
4612 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
4845 u32 tmp;
4848 tmp = RREG32(GRBM_STATUS);
4849 if (tmp & (PA_BUSY | SC_BUSY |
4857 if (tmp & (CP_BUSY | CP_COHERENCY_BUSY))
4861 tmp = RREG32(GRBM_STATUS2);
4862 if (tmp & RLC_BUSY)
4866 tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
4867 if (!(tmp & SDMA_IDLE))
4871 tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
4872 if (!(tmp & SDMA_IDLE))
4876 tmp = RREG32(SRBM_STATUS2);
4877 if (tmp & SDMA_BUSY)
4880 if (tmp & SDMA1_BUSY)
4884 tmp = RREG32(SRBM_STATUS);
4886 if (tmp & IH_BUSY)
4889 if (tmp & SEM_BUSY)
4892 if (tmp & GRBM_RQ_PENDING)
4895 if (tmp & VMC_BUSY)
4898 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
4926 u32 tmp;
4954 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
4955 tmp |= SDMA_HALT;
4956 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
4960 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
4961 tmp |= SDMA_HALT;
4962 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
5009 tmp = RREG32(GRBM_SOFT_RESET);
5010 tmp |= grbm_soft_reset;
5011 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5012 WREG32(GRBM_SOFT_RESET, tmp);
5013 tmp = RREG32(GRBM_SOFT_RESET);
5017 tmp &= ~grbm_soft_reset;
5018 WREG32(GRBM_SOFT_RESET, tmp);
5019 tmp = RREG32(GRBM_SOFT_RESET);
5023 tmp = RREG32(SRBM_SOFT_RESET);
5024 tmp |= srbm_soft_reset;
5025 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
5026 WREG32(SRBM_SOFT_RESET, tmp);
5027 tmp = RREG32(SRBM_SOFT_RESET);
5031 tmp &= ~srbm_soft_reset;
5032 WREG32(SRBM_SOFT_RESET, tmp);
5033 tmp = RREG32(SRBM_SOFT_RESET);
5140 u32 tmp, i;
5157 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
5158 tmp |= SDMA_HALT;
5159 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
5161 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
5162 tmp |= SDMA_HALT;
5163 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
5274 u32 tmp;
5300 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
5301 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
5302 WREG32(MC_VM_FB_LOCATION, tmp);
5330 u32 tmp;
5335 tmp = RREG32(MC_ARB_RAMCFG);
5336 if (tmp & CHANSIZE_MASK) {
5341 tmp = RREG32(MC_SHARED_CHMAP);
5342 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
5496 u32 tmp = RREG32(CHUB_CONTROL);
5497 tmp &= ~BYPASS_VM;
5498 WREG32(CHUB_CONTROL, tmp);
5621 u64 tmp = RREG32(MC_VM_FB_OFFSET);
5622 tmp <<= 22;
5623 rdev->vm_manager.vram_base_offset = tmp;
5760 u32 tmp = RREG32(CP_INT_CNTL_RING0);
5763 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5765 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5766 WREG32(CP_INT_CNTL_RING0, tmp);
5771 u32 tmp;
5773 tmp = RREG32(RLC_LB_CNTL);
5775 tmp |= LOAD_BALANCE_ENABLE;
5777 tmp &= ~LOAD_BALANCE_ENABLE;
5778 WREG32(RLC_LB_CNTL, tmp);
5808 u32 tmp;
5810 tmp = RREG32(RLC_CNTL);
5811 if (tmp != rlc)
5841 u32 tmp, i, mask;
5843 tmp = REQ | MESSAGE(MSG_ENTER_RLC_SAFE_MODE);
5844 WREG32(RLC_GPR_REG2, tmp);
5862 u32 tmp;
5864 tmp = REQ | MESSAGE(MSG_EXIT_RLC_SAFE_MODE);
5865 WREG32(RLC_GPR_REG2, tmp);
5911 u32 i, size, tmp;
5919 tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc;
5920 WREG32(RLC_CGCG_CGLS_CTRL, tmp);
5992 u32 data, orig, tmp, tmp2;
5999 tmp = cik_halt_rlc(rdev);
6007 cik_update_rlc(rdev, tmp);
6028 u32 data, orig, tmp = 0;
6046 tmp = cik_halt_rlc(rdev);
6054 cik_update_rlc(rdev, tmp);
6094 tmp = cik_halt_rlc(rdev);
6102 cik_update_rlc(rdev, tmp);
6526 u32 mask = 0, tmp, tmp1;
6530 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
6534 tmp &= 0xffff0000;
6536 tmp |= tmp1;
6537 tmp >>= 16;
6544 return (~tmp) & mask;
6551 u32 tmp = 0;
6568 tmp |= (cu_bitmap << (i * 16 + j * 8));
6572 WREG32(RLC_PG_AO_CU_MASK, tmp);
6574 tmp = RREG32(RLC_MAX_PG_CU);
6575 tmp &= ~MAX_PU_CU_MASK;
6576 tmp |= MAX_PU_CU(active_cu_number);
6577 WREG32(RLC_MAX_PG_CU, tmp);
6856 u32 tmp;
6859 tmp = RREG32(CP_INT_CNTL_RING0) &
6861 WREG32(CP_INT_CNTL_RING0, tmp);
6863 tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
6864 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);
6865 tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
6866 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp);
6909 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6910 WREG32(DC_HPD1_INT_CONTROL, tmp);
6911 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6912 WREG32(DC_HPD2_INT_CONTROL, tmp);
6913 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6914 WREG32(DC_HPD3_INT_CONTROL, tmp);
6915 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6916 WREG32(DC_HPD4_INT_CONTROL, tmp);
6917 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6918 WREG32(DC_HPD5_INT_CONTROL, tmp);
6919 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6920 WREG32(DC_HPD6_INT_CONTROL, tmp);
7287 u32 tmp;
7364 tmp = RREG32(DC_HPD1_INT_CONTROL);
7365 tmp |= DC_HPDx_INT_ACK;
7366 WREG32(DC_HPD1_INT_CONTROL, tmp);
7369 tmp = RREG32(DC_HPD2_INT_CONTROL);
7370 tmp |= DC_HPDx_INT_ACK;
7371 WREG32(DC_HPD2_INT_CONTROL, tmp);
7374 tmp = RREG32(DC_HPD3_INT_CONTROL);
7375 tmp |= DC_HPDx_INT_ACK;
7376 WREG32(DC_HPD3_INT_CONTROL, tmp);
7379 tmp = RREG32(DC_HPD4_INT_CONTROL);
7380 tmp |= DC_HPDx_INT_ACK;
7381 WREG32(DC_HPD4_INT_CONTROL, tmp);
7384 tmp = RREG32(DC_HPD5_INT_CONTROL);
7385 tmp |= DC_HPDx_INT_ACK;
7386 WREG32(DC_HPD5_INT_CONTROL, tmp);
7389 tmp = RREG32(DC_HPD6_INT_CONTROL);
7390 tmp |= DC_HPDx_INT_ACK;
7391 WREG32(DC_HPD6_INT_CONTROL, tmp);
7394 tmp = RREG32(DC_HPD1_INT_CONTROL);
7395 tmp |= DC_HPDx_RX_INT_ACK;
7396 WREG32(DC_HPD1_INT_CONTROL, tmp);
7399 tmp = RREG32(DC_HPD2_INT_CONTROL);
7400 tmp |= DC_HPDx_RX_INT_ACK;
7401 WREG32(DC_HPD2_INT_CONTROL, tmp);
7404 tmp = RREG32(DC_HPD3_INT_CONTROL);
7405 tmp |= DC_HPDx_RX_INT_ACK;
7406 WREG32(DC_HPD3_INT_CONTROL, tmp);
7409 tmp = RREG32(DC_HPD4_INT_CONTROL);
7410 tmp |= DC_HPDx_RX_INT_ACK;
7411 WREG32(DC_HPD4_INT_CONTROL, tmp);
7414 tmp = RREG32(DC_HPD5_INT_CONTROL);
7415 tmp |= DC_HPDx_RX_INT_ACK;
7416 WREG32(DC_HPD5_INT_CONTROL, tmp);
7419 tmp = RREG32(DC_HPD6_INT_CONTROL);
7420 tmp |= DC_HPDx_RX_INT_ACK;
7421 WREG32(DC_HPD6_INT_CONTROL, tmp);
7483 u32 wptr, tmp;
7499 tmp = RREG32(IH_RB_CNTL);
7500 tmp |= IH_WPTR_OVERFLOW_CLEAR;
7501 WREG32(IH_RB_CNTL, tmp);
8731 u32 tmp = 0;
8756 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
8759 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(0));
8764 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
8768 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(1));
8773 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
8777 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(2));
8784 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
8804 u32 tmp, buffer_alloc, i;
8816 tmp = 1;
8819 tmp = 2;
8822 tmp = 0;
8826 tmp = 0;
8830 tmp = 1;
8835 LB_MEMORY_CONFIG(tmp) | LB_MEMORY_SIZE(0x6B0));
8847 switch (tmp) {
8873 u32 tmp = RREG32(MC_SHARED_CHMAP);
8875 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
9105 u32 tmp, dmif_size = 12288;
9124 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
9125 tmp = min(dfixed_trunc(a), tmp);
9127 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
9238 u32 tmp, wm_mask;
9333 tmp = wm_mask;
9334 tmp &= ~LATENCY_WATERMARK_MASK(3);
9335 tmp |= LATENCY_WATERMARK_MASK(1);
9336 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
9341 tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
9342 tmp &= ~LATENCY_WATERMARK_MASK(3);
9343 tmp |= LATENCY_WATERMARK_MASK(2);
9344 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
9412 uint32_t tmp;
9419 tmp = RREG32_SMC(cntl_reg);
9420 tmp &= ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK);
9421 tmp |= dividers.post_divider;
9422 WREG32_SMC(cntl_reg, tmp);
9451 u32 tmp;
9466 tmp = RREG32_SMC(CG_ECLK_CNTL);
9467 tmp &= ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK);
9468 tmp |= dividers.post_divider;
9469 WREG32_SMC(CG_ECLK_CNTL, tmp);
9535 u32 max_lw, current_lw, tmp;
9540 tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
9541 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
9542 current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
9545 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9546 if (tmp & LC_RENEGOTIATION_SUPPORT) {
9547 tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
9548 tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
9549 tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
9550 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
9574 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
9575 tmp |= LC_SET_QUIESCE;
9576 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
9578 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
9579 tmp |= LC_REDO_EQ;
9580 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
9618 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
9619 tmp &= ~LC_SET_QUIESCE;
9620 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);