Lines Matching defs:queue_state
4494 struct hqd_registers queue_state;
4615 mqd->queue_state.cp_hqd_pq_doorbell_control =
4618 mqd->queue_state.cp_hqd_pq_doorbell_control |= DOORBELL_EN;
4620 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~DOORBELL_EN;
4622 mqd->queue_state.cp_hqd_pq_doorbell_control);
4625 mqd->queue_state.cp_hqd_dequeue_request = 0;
4626 mqd->queue_state.cp_hqd_pq_rptr = 0;
4627 mqd->queue_state.cp_hqd_pq_wptr= 0;
4635 WREG32(CP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
4636 WREG32(CP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
4637 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
4641 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
4642 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
4643 WREG32(CP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
4644 WREG32(CP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
4646 mqd->queue_state.cp_mqd_control = RREG32(CP_MQD_CONTROL);
4647 mqd->queue_state.cp_mqd_control &= ~MQD_VMID_MASK;
4648 WREG32(CP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
4652 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
4653 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
4654 WREG32(CP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
4655 WREG32(CP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
4658 mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL);
4659 mqd->queue_state.cp_hqd_pq_control &=
4662 mqd->queue_state.cp_hqd_pq_control |=
4664 mqd->queue_state.cp_hqd_pq_control |=
4667 mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT;
4669 mqd->queue_state.cp_hqd_pq_control &=
4671 mqd->queue_state.cp_hqd_pq_control |=
4673 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
4680 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
4681 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4682 WREG32(CP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
4684 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
4691 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
4692 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
4695 mqd->queue_state.cp_hqd_pq_rptr_report_addr);
4697 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
4701 mqd->queue_state.cp_hqd_pq_doorbell_control =
4703 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~DOORBELL_OFFSET_MASK;
4704 mqd->queue_state.cp_hqd_pq_doorbell_control |=
4706 mqd->queue_state.cp_hqd_pq_doorbell_control |= DOORBELL_EN;
4707 mqd->queue_state.cp_hqd_pq_doorbell_control &=
4711 mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
4714 mqd->queue_state.cp_hqd_pq_doorbell_control);
4718 mqd->queue_state.cp_hqd_pq_wptr = rdev->ring[idx].wptr;
4719 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
4720 mqd->queue_state.cp_hqd_pq_rptr = RREG32(CP_HQD_PQ_RPTR);
4723 mqd->queue_state.cp_hqd_vmid = 0;
4724 WREG32(CP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
4727 mqd->queue_state.cp_hqd_active = 1;
4728 WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);