Lines Matching defs:pipe
1833 * @pipe: pipe
1839 * me/pipe/queue combination.
1842 u32 me, u32 pipe, u32 queue, u32 vmid)
1844 u32 srbm_gfx_cntl = (PIPEID(pipe & 0x3) |
3011 DRM_ERROR("unknown num pipe config: 0x%x\n", num_pipe_configs);
3506 ref_and_mask = CP2 << ring->pipe;
3509 ref_and_mask = CP6 << ring->pipe;
3547 * event down the pipe with seq one below.
3560 /* Then send the real EOP event down the pipe. */
3851 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
4148 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
4167 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
4189 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
4534 int pipe = (i < 4) ? i : (i - 4);
4536 cik_srbm_select(rdev, me, pipe, 0, 0);
4606 rdev->ring[idx].pipe,
7069 switch (ring->pipe) {
7083 DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe);
7087 switch (ring->pipe) {
7101 DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe);
7112 switch (ring->pipe) {
7126 DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe);
7130 switch (ring->pipe) {
7144 DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe);
7940 if ((cp1_ring->me == me_id) & (cp1_ring->pipe == pipe_id))
7942 if ((cp2_ring->me == me_id) & (cp2_ring->pipe == pipe_id))
8411 ring->pipe = 0; /* first pipe */
8423 ring->pipe = 0; /* first pipe */
8910 u32 lb_size; /* line buffer allocated to pipe */
9100 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */