Lines Matching refs:ret
327 int ret;
329 ret = ci_read_smc_sram_dword(rdev,
335 if (ret)
458 int ret;
461 ret = ci_read_smc_sram_dword(rdev,
465 if (ret)
466 return ret;
467 ret = ci_populate_bapm_vddc_vid_sidd(rdev);
468 if (ret)
469 return ret;
470 ret = ci_populate_vddc_vid(rdev);
471 if (ret)
472 return ret;
473 ret = ci_populate_svi_load_line(rdev);
474 if (ret)
475 return ret;
476 ret = ci_populate_tdc_limit(rdev);
477 if (ret)
478 return ret;
479 ret = ci_populate_dw8(rdev);
480 if (ret)
481 return ret;
482 ret = ci_populate_fuzzy_fan(rdev);
483 if (ret)
484 return ret;
485 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
486 if (ret)
487 return ret;
488 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
489 if (ret)
490 return ret;
491 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
494 if (ret)
495 return ret;
594 int ret;
601 ret = ci_program_pt_config_registers(rdev, didt_config_ci);
602 if (ret) {
604 return ret;
620 int ret = 0;
628 ret = -EINVAL;
636 ret = -EINVAL;
644 ret = -EINVAL;
671 return ret;
678 int ret = 0;
684 ret = -EINVAL;
695 return ret;
724 int ret = 0;
733 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
736 return ret;
940 int ret;
995 ret = ci_copy_bytes_to_smc(rdev,
1001 if (ret) {
1012 PPSMC_Result ret;
1015 ret = ci_send_msg_to_smc_with_parameter(rdev,
1018 if (ret != PPSMC_Result_OK)
1020 ret = ci_send_msg_to_smc_with_parameter(rdev,
1023 if (ret != PPSMC_Result_OK)
1026 ret = ci_send_msg_to_smc_with_parameter(rdev,
1029 if (ret != PPSMC_Result_OK)
1039 PPSMC_Result ret;
1042 ret = ci_send_msg_to_smc(rdev, PPSMC_StopFanControl);
1043 if (ret == PPSMC_Result_OK) {
1230 int ret;
1233 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1234 if (ret)
1235 return ret;
1236 ret = ci_thermal_enable_alert(rdev, true);
1237 if (ret)
1238 return ret;
1240 ret = ci_thermal_setup_fan_table(rdev);
1241 if (ret)
1242 return ret;
1296 int ret = 0;
1302 ret = ci_copy_bytes_to_smc(rdev,
1310 return ret;
1493 int ret;
1512 ret = ci_enable_sclk_mclk_dpm(rdev, true);
1513 if (ret)
1514 return ret;
1554 int ret;
1571 ret = ci_enable_sclk_mclk_dpm(rdev, false);
1572 if (ret)
1573 return ret;
1783 int ret;
1785 ret = ci_read_smc_sram_dword(rdev,
1789 if (ret)
1790 return ret;
1794 ret = ci_read_smc_sram_dword(rdev,
1798 if (ret)
1799 return ret;
1803 ret = ci_read_smc_sram_dword(rdev,
1807 if (ret)
1808 return ret;
1812 ret = ci_read_smc_sram_dword(rdev,
1816 if (ret)
1817 return ret;
1821 ret = ci_read_smc_sram_dword(rdev,
1825 if (ret)
1826 return ret;
2098 int ret;
2101 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
2104 if (ret)
2105 return ret;
2107 ret = ci_get_svi2_voltage_table(rdev,
2110 if (ret)
2111 return ret;
2119 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
2122 if (ret)
2123 return ret;
2125 ret = ci_get_svi2_voltage_table(rdev,
2128 if (ret)
2129 return ret;
2137 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
2140 if (ret)
2141 return ret;
2143 ret = ci_get_svi2_voltage_table(rdev,
2146 if (ret)
2147 return ret;
2161 int ret;
2163 ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
2167 if (ret) {
2251 int ret;
2253 ret = ci_populate_smc_vddc_table(rdev, table);
2254 if (ret)
2255 return ret;
2257 ret = ci_populate_smc_vddci_table(rdev, table);
2258 if (ret)
2259 return ret;
2261 ret = ci_populate_smc_mvdd_table(rdev, table);
2262 if (ret)
2263 return ret;
2378 int ret;
2380 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
2382 if (ret)
2383 return ret;
2512 int ret = 0;
2518 ret = ci_populate_memory_timing_parameters(rdev,
2522 if (ret)
2527 if (ret == 0)
2528 ret = ci_copy_bytes_to_smc(rdev,
2534 return ret;
2614 int ret = -EINVAL;
2628 ret = radeon_atom_get_clock_dividers(rdev,
2631 if (ret)
2632 return ret;
2636 ret = radeon_atom_get_clock_dividers(rdev,
2639 if (ret)
2640 return ret;
2649 return ret;
2657 int ret = -EINVAL;
2669 ret = radeon_atom_get_clock_dividers(rdev,
2672 if (ret)
2673 return ret;
2681 return ret;
2690 int ret = -EINVAL;
2702 ret = radeon_atom_get_clock_dividers(rdev,
2705 if (ret)
2706 return ret;
2714 return ret;
2722 int ret = -EINVAL;
2734 ret = radeon_atom_get_clock_dividers(rdev,
2737 if (ret)
2738 return ret;
2746 return ret;
2766 int ret;
2768 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2769 if (ret)
2770 return ret;
2841 int ret;
2845 ret = ci_get_dependency_volt_by_clk(rdev,
2848 if (ret)
2849 return ret;
2853 ret = ci_get_dependency_volt_by_clk(rdev,
2856 if (ret)
2857 return ret;
2861 ret = ci_get_dependency_volt_by_clk(rdev,
2864 if (ret)
2865 return ret;
2926 ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
2927 if (ret)
2928 return ret;
2960 int ret;
2973 ret = radeon_atom_get_clock_dividers(rdev,
2976 if (ret)
2977 return ret;
3133 int ret;
3135 ret = radeon_atom_get_clock_dividers(rdev,
3138 if (ret)
3139 return ret;
3182 int ret;
3184 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
3185 if (ret)
3186 return ret;
3188 ret = ci_get_dependency_volt_by_clk(rdev,
3191 if (ret)
3192 return ret;
3246 u32 i, ret;
3251 ret = ci_populate_single_graphic_level(rdev,
3255 if (ret)
3256 return ret;
3269 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
3272 if (ret)
3273 return ret;
3293 u32 i, ret;
3300 ret = ci_populate_single_memory_level(rdev,
3303 if (ret)
3304 return ret;
3326 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
3329 if (ret)
3330 return ret;
3504 int ret = -EINVAL;
3509 ret = 0;
3513 return ret;
3522 int ret;
3524 ret = ci_setup_default_dpm_tables(rdev);
3525 if (ret)
3526 return ret;
3543 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);
3544 if (ret)
3545 return ret;
3549 ret = ci_populate_all_graphic_levels(rdev);
3550 if (ret)
3551 return ret;
3553 ret = ci_populate_all_memory_levels(rdev);
3554 if (ret)
3555 return ret;
3559 ret = ci_populate_smc_acpi_level(rdev, table);
3560 if (ret)
3561 return ret;
3563 ret = ci_populate_smc_vce_level(rdev, table);
3564 if (ret)
3565 return ret;
3567 ret = ci_populate_smc_acp_level(rdev, table);
3568 if (ret)
3569 return ret;
3571 ret = ci_populate_smc_samu_level(rdev, table);
3572 if (ret)
3573 return ret;
3575 ret = ci_do_program_memory_timing_parameters(rdev);
3576 if (ret)
3577 return ret;
3579 ret = ci_populate_smc_uvd_level(rdev, table);
3580 if (ret)
3581 return ret;
3590 ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3594 ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3604 ret = ci_populate_bapm_parameters_in_dpm_table(rdev);
3605 if (ret)
3606 return ret;
3652 ret = ci_copy_bytes_to_smc(rdev,
3658 if (ret)
3659 return ret;
3866 int ret;
3878 ret = ci_populate_all_graphic_levels(rdev);
3879 if (ret)
3880 return ret;
3884 ret = ci_populate_all_memory_levels(rdev);
3885 if (ret)
3886 return ret;
4080 int ret = 0;
4094 ret = ci_enable_vce_dpm(rdev, true);
4099 ret = ci_enable_vce_dpm(rdev, false);
4102 return ret;
4133 int ret;
4135 ret = ci_trim_dpm_states(rdev, radeon_state);
4136 if (ret)
4137 return ret;
4172 int ret;
4182 ret = ci_dpm_force_state_pcie(rdev, level);
4183 if (ret)
4184 return ret;
4201 ret = ci_dpm_force_state_sclk(rdev, levels);
4202 if (ret)
4203 return ret;
4220 ret = ci_dpm_force_state_mclk(rdev, levels);
4221 if (ret)
4222 return ret;
4237 ret = ci_dpm_force_state_sclk(rdev, levels);
4238 if (ret)
4239 return ret;
4252 ret = ci_dpm_force_state_mclk(rdev, levels);
4253 if (ret)
4254 return ret;
4267 ret = ci_dpm_force_state_pcie(rdev, levels);
4268 if (ret)
4269 return ret;
4287 ret = ci_upload_dpm_level_enable_mask(rdev);
4288 if (ret)
4289 return ret;
4591 int ret;
4618 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4619 if (ret)
4622 ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4623 if (ret)
4628 ret = ci_register_patching_mc_seq(rdev, ci_table);
4629 if (ret)
4632 ret = ci_set_mc_special_registers(rdev, ci_table);
4633 if (ret)
4641 return ret;
4714 int ret;
4718 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);
4719 if (ret)
4720 return ret;
5130 int ret;
5136 ret = ci_construct_voltage_tables(rdev);
5137 if (ret) {
5139 return ret;
5143 ret = ci_initialize_mc_reg_table(rdev);
5144 if (ret)
5154 ret = ci_upload_firmware(rdev);
5155 if (ret) {
5157 return ret;
5159 ret = ci_process_firmware_header(rdev);
5160 if (ret) {
5162 return ret;
5164 ret = ci_initial_switch_from_arb_f0_to_f1(rdev);
5165 if (ret) {
5167 return ret;
5169 ret = ci_init_smc_table(rdev);
5170 if (ret) {
5172 return ret;
5174 ret = ci_init_arb_table_index(rdev);
5175 if (ret) {
5177 return ret;
5180 ret = ci_populate_initial_mc_reg_table(rdev);
5181 if (ret) {
5183 return ret;
5186 ret = ci_populate_pm_base(rdev);
5187 if (ret) {
5189 return ret;
5193 ret = ci_notify_smc_display_change(rdev, false);
5194 if (ret) {
5196 return ret;
5199 ret = ci_enable_ulv(rdev, true);
5200 if (ret) {
5202 return ret;
5204 ret = ci_enable_ds_master_switch(rdev, true);
5205 if (ret) {
5207 return ret;
5209 ret = ci_start_dpm(rdev);
5210 if (ret) {
5212 return ret;
5214 ret = ci_enable_didt(rdev, true);
5215 if (ret) {
5217 return ret;
5219 ret = ci_enable_smc_cac(rdev, true);
5220 if (ret) {
5222 return ret;
5224 ret = ci_enable_power_containment(rdev, true);
5225 if (ret) {
5227 return ret;
5230 ret = ci_power_control_set_level(rdev);
5231 if (ret) {
5233 return ret;
5238 ret = ci_enable_thermal_based_sclk_dpm(rdev, true);
5239 if (ret) {
5241 return ret;
5253 int ret;
5255 ret = ci_thermal_enable_alert(rdev, false);
5256 if (ret)
5257 return ret;
5258 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
5259 if (ret)
5260 return ret;
5261 ret = ci_thermal_enable_alert(rdev, true);
5262 if (ret)
5263 return ret;
5265 return ret;
5270 int ret;
5272 ret = ci_set_temperature_range(rdev);
5273 if (ret)
5274 return ret;
5317 int ret;
5322 ret = ci_freeze_sclk_mclk_dpm(rdev);
5323 if (ret) {
5325 return ret;
5327 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps);
5328 if (ret) {
5330 return ret;
5332 ret = ci_generate_dpm_level_enable_mask(rdev, new_ps);
5333 if (ret) {
5335 return ret;
5338 ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
5339 if (ret) {
5341 return ret;
5344 ret = ci_update_sclk_t(rdev);
5345 if (ret) {
5347 return ret;
5350 ret = ci_update_and_upload_mc_reg_table(rdev);
5351 if (ret) {
5353 return ret;
5356 ret = ci_program_memory_timing_parameters(rdev);
5357 if (ret) {
5359 return ret;
5361 ret = ci_unfreeze_sclk_mclk_dpm(rdev);
5362 if (ret) {
5364 return ret;
5366 ret = ci_upload_dpm_level_enable_mask(rdev);
5367 if (ret) {
5369 return ret;
5520 int ret;
5551 ret = -EINVAL;
5556 ret = -ENOMEM;
5603 return ret;
5656 int ret;
5690 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
5691 if (ret) {
5693 return ret;
5696 ret = r600_get_platform_caps(rdev);
5697 if (ret) {
5699 return ret;
5702 ret = r600_parse_extended_power_table(rdev);
5703 if (ret) {
5705 return ret;
5708 ret = ci_parse_power_table(rdev);
5709 if (ret) {
5712 return ret;