Lines Matching refs:UvdLevel
2620 table->UvdLevel[count].VclkFrequency =
2622 table->UvdLevel[count].DclkFrequency =
2624 table->UvdLevel[count].MinVddc =
2626 table->UvdLevel[count].MinVddcPhases = 1;
2630 table->UvdLevel[count].VclkFrequency, false, ÷rs);
2634 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2638 table->UvdLevel[count].DclkFrequency, false, ÷rs);
2642 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2644 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2645 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2646 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);