Lines Matching defs:table
1002 DRM_ERROR("Failed to load fan table to the SMC.");
1280 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
1286 table->FpsHighT = cpu_to_be16(tmp);
1289 table->FpsLowT = cpu_to_be16(tmp);
2180 SMU7_Discrete_DpmTable *table)
2185 table->VddcLevelCount = pi->vddc_voltage_table.count;
2186 for (count = 0; count < table->VddcLevelCount; count++) {
2189 &table->VddcLevel[count]);
2192 table->VddcLevel[count].Smio |=
2195 table->VddcLevel[count].Smio = 0;
2197 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
2203 SMU7_Discrete_DpmTable *table)
2208 table->VddciLevelCount = pi->vddci_voltage_table.count;
2209 for (count = 0; count < table->VddciLevelCount; count++) {
2212 &table->VddciLevel[count]);
2215 table->VddciLevel[count].Smio |=
2218 table->VddciLevel[count].Smio = 0;
2220 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
2226 SMU7_Discrete_DpmTable *table)
2231 table->MvddLevelCount = pi->mvdd_voltage_table.count;
2232 for (count = 0; count < table->MvddLevelCount; count++) {
2235 &table->MvddLevel[count]);
2238 table->MvddLevel[count].Smio |=
2241 table->MvddLevel[count].Smio = 0;
2243 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
2249 SMU7_Discrete_DpmTable *table)
2253 ret = ci_populate_smc_vddc_table(rdev, table);
2257 ret = ci_populate_smc_vddci_table(rdev, table);
2261 ret = ci_populate_smc_mvdd_table(rdev, table);
2588 SMU7_Discrete_DpmTable *table)
2595 table->LinkLevel[i].PcieGenSpeed =
2597 table->LinkLevel[i].PcieLaneCount =
2599 table->LinkLevel[i].EnabledForActivity = 1;
2600 table->LinkLevel[i].DownT = cpu_to_be32(5);
2601 table->LinkLevel[i].UpT = cpu_to_be32(30);
2610 SMU7_Discrete_DpmTable *table)
2616 table->UvdLevelCount =
2619 for (count = 0; count < table->UvdLevelCount; count++) {
2620 table->UvdLevel[count].VclkFrequency =
2622 table->UvdLevel[count].DclkFrequency =
2624 table->UvdLevel[count].MinVddc =
2626 table->UvdLevel[count].MinVddcPhases = 1;
2630 table->UvdLevel[count].VclkFrequency, false, ÷rs);
2634 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2638 table->UvdLevel[count].DclkFrequency, false, ÷rs);
2642 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2644 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2645 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2646 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2653 SMU7_Discrete_DpmTable *table)
2659 table->VceLevelCount =
2662 for (count = 0; count < table->VceLevelCount; count++) {
2663 table->VceLevel[count].Frequency =
2665 table->VceLevel[count].MinVoltage =
2667 table->VceLevel[count].MinPhases = 1;
2671 table->VceLevel[count].Frequency, false, ÷rs);
2675 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2677 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2678 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2686 SMU7_Discrete_DpmTable *table)
2692 table->AcpLevelCount = (u8)
2695 for (count = 0; count < table->AcpLevelCount; count++) {
2696 table->AcpLevel[count].Frequency =
2698 table->AcpLevel[count].MinVoltage =
2700 table->AcpLevel[count].MinPhases = 1;
2704 table->AcpLevel[count].Frequency, false, ÷rs);
2708 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2710 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2711 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2718 SMU7_Discrete_DpmTable *table)
2724 table->SamuLevelCount =
2727 for (count = 0; count < table->SamuLevelCount; count++) {
2728 table->SamuLevel[count].Frequency =
2730 table->SamuLevel[count].MinVoltage =
2732 table->SamuLevel[count].MinPhases = 1;
2736 table->SamuLevel[count].Frequency, false, ÷rs);
2740 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2742 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2743 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2951 SMU7_Discrete_DpmTable *table)
2962 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2965 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
2967 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
2969 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
2971 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
2975 table->ACPILevel.SclkFrequency, false, ÷rs);
2979 table->ACPILevel.SclkDid = (u8)dividers.post_divider;
2980 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2981 table->ACPILevel.DeepSleepDivId = 0;
2989 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2990 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2991 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
2992 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
2993 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
2994 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2995 table->ACPILevel.CcPwrDynRm = 0;
2996 table->ACPILevel.CcPwrDynRm1 = 0;
2998 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
2999 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
3000 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
3001 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
3002 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
3003 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
3004 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
3005 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
3006 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
3007 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
3008 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
3010 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
3011 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
3015 table->MemoryACPILevel.MinVddci =
3018 table->MemoryACPILevel.MinVddci =
3023 table->MemoryACPILevel.MinMvdd = 0;
3025 table->MemoryACPILevel.MinMvdd =
3033 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
3034 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
3035 table->MemoryACPILevel.MpllAdFuncCntl =
3037 table->MemoryACPILevel.MpllDqFuncCntl =
3039 table->MemoryACPILevel.MpllFuncCntl =
3041 table->MemoryACPILevel.MpllFuncCntl_1 =
3043 table->MemoryACPILevel.MpllFuncCntl_2 =
3045 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
3046 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
3048 table->MemoryACPILevel.EnabledForThrottle = 0;
3049 table->MemoryACPILevel.EnabledForActivity = 0;
3050 table->MemoryACPILevel.UpH = 0;
3051 table->MemoryACPILevel.DownH = 100;
3052 table->MemoryACPILevel.VoltageDownH = 0;
3053 table->MemoryACPILevel.ActivityLevel =
3056 table->MemoryACPILevel.StutterEnable = false;
3057 table->MemoryACPILevel.StrobeEnable = false;
3058 table->MemoryACPILevel.EdcReadEnable = false;
3059 table->MemoryACPILevel.EdcWriteEnable = false;
3060 table->MemoryACPILevel.RttEnable = false;
3500 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3506 for(i = 0; i < table->count; i++) {
3507 if (value == table->dpm_levels[i].value) {
3521 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3529 ci_populate_smc_voltage_tables(rdev, table);
3534 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3537 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3540 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3557 ci_populate_smc_link_level(rdev, table);
3559 ret = ci_populate_smc_acpi_level(rdev, table);
3563 ret = ci_populate_smc_vce_level(rdev, table);
3567 ret = ci_populate_smc_acp_level(rdev, table);
3571 ret = ci_populate_smc_samu_level(rdev, table);
3579 ret = ci_populate_smc_uvd_level(rdev, table);
3583 table->UvdBootLevel = 0;
3584 table->VceBootLevel = 0;
3585 table->AcpBootLevel = 0;
3586 table->SamuBootLevel = 0;
3587 table->GraphicsBootLevel = 0;
3588 table->MemoryBootLevel = 0;
3598 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3599 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3600 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3608 table->UVDInterval = 1;
3609 table->VCEInterval = 1;
3610 table->ACPInterval = 1;
3611 table->SAMUInterval = 1;
3612 table->GraphicsVoltageChangeEnable = 1;
3613 table->GraphicsThermThrottleEnable = 1;
3614 table->GraphicsInterval = 1;
3615 table->VoltageInterval = 1;
3616 table->ThermalInterval = 1;
3617 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3619 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3621 table->MemoryVoltageChangeEnable = 1;
3622 table->MemoryInterval = 1;
3623 table->VoltageResponseTime = 0;
3624 table->VddcVddciDelta = 4000;
3625 table->PhaseResponseTime = 0;
3626 table->MemoryThermThrottleEnable = 1;
3627 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
3628 table->PCIeGenInterval = 1;
3630 table->SVI2Enable = 1;
3632 table->SVI2Enable = 0;
3634 table->ThermGpio = 17;
3635 table->SclkStepSize = 0x4000;
3637 table->SystemFlags = cpu_to_be32(table->SystemFlags);
3638 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3639 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3640 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3641 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3642 table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3643 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3644 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3645 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3646 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3647 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3648 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3649 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3650 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3655 (u8 *)&table->SystemFlags,
4064 struct radeon_vce_clock_voltage_dependency_table *table =
4067 for (i = 0; i < table->count; i++) {
4068 if (table->entries[i].evclk >= min_evclk)
4072 return table->count - 1;
4298 struct ci_mc_reg_table *table)
4304 for (i = 0, j = table->last; i < table->last; i++) {
4307 switch(table->mc_reg_address[i].s1 << 2) {
4310 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
4311 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
4312 for (k = 0; k < table->num_entries; k++) {
4313 table->mc_reg_table_entry[k].mc_data[j] =
4314 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
4321 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
4322 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
4323 for (k = 0; k < table->num_entries; k++) {
4324 table->mc_reg_table_entry[k].mc_data[j] =
4325 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4327 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
4334 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
4335 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
4336 for (k = 0; k < table->num_entries; k++) {
4337 table->mc_reg_table_entry[k].mc_data[j] =
4338 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
4347 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
4348 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
4349 for (k = 0; k < table->num_entries; k++) {
4350 table->mc_reg_table_entry[k].mc_data[j] =
4351 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4363 table->last = j;
4441 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4445 for (i = 0; i < table->last; i++) {
4446 for (j = 1; j < table->num_entries; j++) {
4447 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4448 table->mc_reg_table_entry[j].mc_data[i]) {
4449 table->valid_flag |= 1 << i;
4456 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4461 for (i = 0; i < table->last; i++) {
4462 table->mc_reg_address[i].s0 =
4463 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4464 address : table->mc_reg_address[i].s1;
4468 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4473 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4475 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4478 for (i = 0; i < table->last; i++)
4479 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4481 ci_table->last = table->last;
4483 for (i = 0; i < table->num_entries; i++) {
4485 table->mc_reg_table_entry[i].mclk_max;
4486 for (j = 0; j < table->last; j++)
4488 table->mc_reg_table_entry[i].mc_data[j];
4490 ci_table->num_entries = table->num_entries;
4496 struct ci_mc_reg_table *table)
4508 for (i = 0; i < table->last; i++) {
4509 if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4511 switch(table->mc_reg_address[i].s1 >> 2) {
4513 for (k = 0; k < table->num_entries; k++) {
4514 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4515 (table->mc_reg_table_entry[k].mclk_max == 137500))
4516 table->mc_reg_table_entry[k].mc_data[i] =
4517 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
4522 for (k = 0; k < table->num_entries; k++) {
4523 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4524 (table->mc_reg_table_entry[k].mclk_max == 137500))
4525 table->mc_reg_table_entry[k].mc_data[i] =
4526 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4531 for (k = 0; k < table->num_entries; k++) {
4532 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4533 (table->mc_reg_table_entry[k].mclk_max == 137500))
4534 table->mc_reg_table_entry[k].mc_data[i] =
4535 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4540 for (k = 0; k < table->num_entries; k++) {
4541 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4542 (table->mc_reg_table_entry[k].mclk_max == 137500))
4543 table->mc_reg_table_entry[k].mc_data[i] = 0;
4547 for (k = 0; k < table->num_entries; k++) {
4548 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4549 table->mc_reg_table_entry[k].mc_data[i] =
4550 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4552 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4553 table->mc_reg_table_entry[k].mc_data[i] =
4554 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4559 for (k = 0; k < table->num_entries; k++) {
4560 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4561 table->mc_reg_table_entry[k].mc_data[i] =
4562 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4564 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4565 table->mc_reg_table_entry[k].mc_data[i] =
4566 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4588 struct atom_mc_reg_table *table;
4593 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4594 if (!table)
4618 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4622 ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4639 kfree(table);
4950 struct radeon_clock_voltage_dependency_table *table)
4954 if (table) {
4955 for (i = 0; i < table->count; i++)
4956 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4961 struct radeon_clock_voltage_dependency_table *table)
4965 if (table) {
4966 for (i = 0; i < table->count; i++)
4967 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
4972 struct radeon_vce_clock_voltage_dependency_table *table)
4976 if (table) {
4977 for (i = 0; i < table->count; i++)
4978 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4983 struct radeon_uvd_clock_voltage_dependency_table *table)
4987 if (table) {
4988 for (i = 0; i < table->count; i++)
4989 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4994 struct radeon_phase_shedding_limits_table *table)
4998 if (table) {
4999 for (i = 0; i < table->count; i++)
5000 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
5005 struct radeon_clock_and_voltage_limits *table)
5007 if (table) {
5008 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);
5009 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);
5014 struct radeon_cac_leakage_table *table)
5018 if (table) {
5019 for (i = 0; i < table->count; i++)
5020 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);