Lines Matching defs:rdev
154 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
155 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
157 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
160 static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
161 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
163 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
165 static PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg);
166 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
169 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev);
170 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev);
172 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev)
174 struct ci_power_info *pi = rdev->pm.dpm.priv;
186 static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
188 struct ci_power_info *pi = ci_get_pi(rdev);
190 switch (rdev->pdev->device) {
237 if (rdev->family == CHIP_HAWAII)
251 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev)
253 struct ci_power_info *pi = ci_get_pi(rdev);
259 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
261 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
263 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
264 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
267 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
268 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
269 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
270 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
271 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
273 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
274 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
280 static int ci_populate_vddc_vid(struct radeon_device *rdev)
282 struct ci_power_info *pi = ci_get_pi(rdev);
295 static int ci_populate_svi_load_line(struct radeon_device *rdev)
297 struct ci_power_info *pi = ci_get_pi(rdev);
308 static int ci_populate_tdc_limit(struct radeon_device *rdev)
310 struct ci_power_info *pi = ci_get_pi(rdev);
314 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
323 static int ci_populate_dw8(struct radeon_device *rdev)
325 struct ci_power_info *pi = ci_get_pi(rdev);
329 ret = ci_read_smc_sram_dword(rdev,
343 static int ci_populate_fuzzy_fan(struct radeon_device *rdev)
345 struct ci_power_info *pi = ci_get_pi(rdev);
347 if ((rdev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
348 (rdev->pm.dpm.fan.fan_output_sensitivity == 0))
349 rdev->pm.dpm.fan.fan_output_sensitivity =
350 rdev->pm.dpm.fan.default_fan_output_sensitivity;
353 cpu_to_be16(rdev->pm.dpm.fan.fan_output_sensitivity);
358 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev)
360 struct ci_power_info *pi = ci_get_pi(rdev);
390 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev)
392 struct ci_power_info *pi = ci_get_pi(rdev);
395 rdev->pm.dpm.dyn_state.cac_tdp_table;
406 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev)
408 struct ci_power_info *pi = ci_get_pi(rdev);
412 rdev->pm.dpm.dyn_state.cac_tdp_table;
413 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
454 static int ci_populate_pm_base(struct radeon_device *rdev)
456 struct ci_power_info *pi = ci_get_pi(rdev);
461 ret = ci_read_smc_sram_dword(rdev,
467 ret = ci_populate_bapm_vddc_vid_sidd(rdev);
470 ret = ci_populate_vddc_vid(rdev);
473 ret = ci_populate_svi_load_line(rdev);
476 ret = ci_populate_tdc_limit(rdev);
479 ret = ci_populate_dw8(rdev);
482 ret = ci_populate_fuzzy_fan(rdev);
485 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
488 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
491 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
501 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
503 struct ci_power_info *pi = ci_get_pi(rdev);
543 static int ci_program_pt_config_registers(struct radeon_device *rdev,
591 static int ci_enable_didt(struct radeon_device *rdev, bool enable)
593 struct ci_power_info *pi = ci_get_pi(rdev);
598 cik_enter_rlc_safe_mode(rdev);
601 ret = ci_program_pt_config_registers(rdev, didt_config_ci);
603 cik_exit_rlc_safe_mode(rdev);
608 ci_do_enable_didt(rdev, enable);
610 cik_exit_rlc_safe_mode(rdev);
616 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
618 struct ci_power_info *pi = ci_get_pi(rdev);
626 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
634 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable);
642 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable);
647 rdev->pm.dpm.dyn_state.cac_tdp_table;
653 ci_set_power_limit(rdev, default_pwr_limit);
660 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable);
663 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
666 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable);
674 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
676 struct ci_power_info *pi = ci_get_pi(rdev);
682 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
690 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
698 static int ci_enable_thermal_based_sclk_dpm(struct radeon_device *rdev,
701 struct ci_power_info *pi = ci_get_pi(rdev);
706 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_ENABLE_THERMAL_DPM);
708 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DISABLE_THERMAL_DPM);
717 static int ci_power_control_set_level(struct radeon_device *rdev)
719 struct ci_power_info *pi = ci_get_pi(rdev);
721 rdev->pm.dpm.dyn_state.cac_tdp_table;
729 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment);
733 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
739 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
741 struct ci_power_info *pi = ci_get_pi(rdev);
748 ci_update_uvd_dpm(rdev, gate);
751 bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
753 struct ci_power_info *pi = ci_get_pi(rdev);
754 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
760 if (r600_dpm_get_vrefresh(rdev) > 120)
770 static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
774 struct ci_power_info *pi = ci_get_pi(rdev);
781 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
782 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
788 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
789 ci_dpm_vblank_too_short(rdev))
799 if (rdev->pm.dpm.ac_power)
800 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
802 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
804 if (rdev->pm.dpm.ac_power == false) {
824 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
825 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
826 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
827 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
845 static int ci_thermal_set_temperature_range(struct radeon_device *rdev,
875 rdev->pm.dpm.thermal.min_temp = low_temp;
876 rdev->pm.dpm.thermal.max_temp = high_temp;
881 static int ci_thermal_enable_alert(struct radeon_device *rdev,
890 rdev->irq.dpm_thermal = false;
891 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Enable);
899 rdev->irq.dpm_thermal = true;
900 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Disable);
910 static void ci_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
912 struct ci_power_info *pi = ci_get_pi(rdev);
932 static int ci_thermal_setup_fan_table(struct radeon_device *rdev)
934 struct ci_power_info *pi = ci_get_pi(rdev);
944 rdev->pm.dpm.fan.ucode_fan_control = false;
951 rdev->pm.dpm.fan.ucode_fan_control = false;
955 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
959 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
960 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
962 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
963 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
968 fan_table.TempMin = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
969 fan_table.TempMed = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
970 fan_table.TempMax = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
977 fan_table.HystDown = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
985 reference_clock = radeon_get_xclk(rdev);
987 fan_table.RefreshPeriod = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
995 ret = ci_copy_bytes_to_smc(rdev,
1003 rdev->pm.dpm.fan.ucode_fan_control = false;
1009 static int ci_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
1011 struct ci_power_info *pi = ci_get_pi(rdev);
1015 ret = ci_send_msg_to_smc_with_parameter(rdev,
1020 ret = ci_send_msg_to_smc_with_parameter(rdev,
1022 rdev->pm.dpm.fan.default_max_fan_pwm);
1026 ret = ci_send_msg_to_smc_with_parameter(rdev,
1037 static int ci_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
1040 struct ci_power_info *pi = ci_get_pi(rdev);
1042 ret = ci_send_msg_to_smc(rdev, PPSMC_StopFanControl);
1050 int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
1056 if (rdev->pm.no_fan)
1075 int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
1081 struct ci_power_info *pi = ci_get_pi(rdev);
1083 if (rdev->pm.no_fan)
1108 void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
1112 if (rdev->pm.dpm.fan.ucode_fan_control)
1113 ci_fan_ctrl_stop_smc_fan_control(rdev);
1114 ci_fan_ctrl_set_static_mode(rdev, mode);
1117 if (rdev->pm.dpm.fan.ucode_fan_control)
1118 ci_thermal_start_smc_fan_control(rdev);
1120 ci_fan_ctrl_set_default_mode(rdev);
1124 u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev)
1126 struct ci_power_info *pi = ci_get_pi(rdev);
1137 static int ci_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
1141 u32 xclk = radeon_get_xclk(rdev);
1143 if (rdev->pm.no_fan)
1146 if (rdev->pm.fan_pulses_per_revolution == 0)
1158 static int ci_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
1162 u32 xclk = radeon_get_xclk(rdev);
1164 if (rdev->pm.no_fan)
1167 if (rdev->pm.fan_pulses_per_revolution == 0)
1170 if ((speed < rdev->pm.fan_min_rpm) ||
1171 (speed > rdev->pm.fan_max_rpm))
1174 if (rdev->pm.dpm.fan.ucode_fan_control)
1175 ci_fan_ctrl_stop_smc_fan_control(rdev);
1182 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
1188 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev)
1190 struct ci_power_info *pi = ci_get_pi(rdev);
1205 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev)
1207 if (rdev->pm.dpm.fan.ucode_fan_control) {
1208 ci_fan_ctrl_start_smc_fan_control(rdev);
1209 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
1213 static void ci_thermal_initialize(struct radeon_device *rdev)
1217 if (rdev->pm.fan_pulses_per_revolution) {
1219 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
1228 static int ci_thermal_start_thermal_controller(struct radeon_device *rdev)
1232 ci_thermal_initialize(rdev);
1233 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1236 ret = ci_thermal_enable_alert(rdev, true);
1239 if (rdev->pm.dpm.fan.ucode_fan_control) {
1240 ret = ci_thermal_setup_fan_table(rdev);
1243 ci_thermal_start_smc_fan_control(rdev);
1249 static void ci_thermal_stop_thermal_controller(struct radeon_device *rdev)
1251 if (!rdev->pm.no_fan)
1252 ci_fan_ctrl_set_default_mode(rdev);
1256 static int ci_read_smc_soft_register(struct radeon_device *rdev,
1259 struct ci_power_info *pi = ci_get_pi(rdev);
1261 return ci_read_smc_sram_dword(rdev,
1267 static int ci_write_smc_soft_register(struct radeon_device *rdev,
1270 struct ci_power_info *pi = ci_get_pi(rdev);
1272 return ci_write_smc_sram_dword(rdev,
1277 static void ci_init_fps_limits(struct radeon_device *rdev)
1279 struct ci_power_info *pi = ci_get_pi(rdev);
1293 static int ci_update_sclk_t(struct radeon_device *rdev)
1295 struct ci_power_info *pi = ci_get_pi(rdev);
1302 ret = ci_copy_bytes_to_smc(rdev,
1313 static void ci_get_leakage_voltages(struct radeon_device *rdev)
1315 struct ci_power_info *pi = ci_get_pi(rdev);
1323 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1326 if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0)
1334 } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
1337 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
1355 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
1357 struct ci_power_info *pi = ci_get_pi(rdev);
1392 static void ci_enable_auto_throttle_source(struct radeon_device *rdev,
1396 struct ci_power_info *pi = ci_get_pi(rdev);
1401 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1406 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1411 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev)
1413 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1414 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1417 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev)
1419 struct ci_power_info *pi = ci_get_pi(rdev);
1427 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1434 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1443 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
1445 struct ci_power_info *pi = ci_get_pi(rdev);
1450 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable);
1456 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable);
1474 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable);
1480 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable);
1489 static int ci_start_dpm(struct radeon_device *rdev)
1491 struct ci_power_info *pi = ci_get_pi(rdev);
1504 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1508 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable);
1512 ret = ci_enable_sclk_mclk_dpm(rdev, true);
1517 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable);
1525 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev)
1527 struct ci_power_info *pi = ci_get_pi(rdev);
1535 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1542 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1550 static int ci_stop_dpm(struct radeon_device *rdev)
1552 struct ci_power_info *pi = ci_get_pi(rdev);
1566 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable);
1571 ret = ci_enable_sclk_mclk_dpm(rdev, false);
1575 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable);
1582 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
1594 static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1597 struct ci_power_info *pi = ci_get_pi(rdev);
1599 rdev->pm.dpm.dyn_state.cac_tdp_table;
1607 ci_set_power_limit(rdev, power_limit);
1611 ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1613 ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1620 static PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg)
1625 if (!ci_is_smc_running(rdev))
1630 for (i = 0; i < rdev->usec_timeout; i++) {
1641 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1645 return ci_send_msg_to_smc(rdev, msg);
1648 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev,
1653 smc_result = ci_send_msg_to_smc(rdev, msg);
1661 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
1663 struct ci_power_info *pi = ci_get_pi(rdev);
1667 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1675 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
1677 struct ci_power_info *pi = ci_get_pi(rdev);
1681 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1689 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)
1691 struct ci_power_info *pi = ci_get_pi(rdev);
1695 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1703 static int ci_set_power_limit(struct radeon_device *rdev, u32 n)
1705 struct ci_power_info *pi = ci_get_pi(rdev);
1709 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n);
1717 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
1721 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1728 static int ci_set_boot_state(struct radeon_device *rdev)
1730 return ci_enable_sclk_mclk_dpm(rdev, false);
1734 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
1738 ci_send_msg_to_smc_return_parameter(rdev,
1747 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)
1751 ci_send_msg_to_smc_return_parameter(rdev,
1760 static void ci_dpm_start_smc(struct radeon_device *rdev)
1764 ci_program_jump_on_start(rdev);
1765 ci_start_smc_clock(rdev);
1766 ci_start_smc(rdev);
1767 for (i = 0; i < rdev->usec_timeout; i++) {
1773 static void ci_dpm_stop_smc(struct radeon_device *rdev)
1775 ci_reset_smc(rdev);
1776 ci_stop_smc_clock(rdev);
1779 static int ci_process_firmware_header(struct radeon_device *rdev)
1781 struct ci_power_info *pi = ci_get_pi(rdev);
1785 ret = ci_read_smc_sram_dword(rdev,
1794 ret = ci_read_smc_sram_dword(rdev,
1803 ret = ci_read_smc_sram_dword(rdev,
1812 ret = ci_read_smc_sram_dword(rdev,
1821 ret = ci_read_smc_sram_dword(rdev,
1833 static void ci_read_clock_registers(struct radeon_device *rdev)
1835 struct ci_power_info *pi = ci_get_pi(rdev);
1860 static void ci_init_sclk_t(struct radeon_device *rdev)
1862 struct ci_power_info *pi = ci_get_pi(rdev);
1867 static void ci_enable_thermal_protection(struct radeon_device *rdev,
1879 static void ci_enable_acpi_power_management(struct radeon_device *rdev)
1889 static int ci_enter_ulp_state(struct radeon_device *rdev)
1899 static int ci_exit_ulp_state(struct radeon_device *rdev)
1907 for (i = 0; i < rdev->usec_timeout; i++) {
1917 static int ci_notify_smc_display_change(struct radeon_device *rdev,
1922 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL;
1925 static int ci_enable_ds_master_switch(struct radeon_device *rdev,
1928 struct ci_power_info *pi = ci_get_pi(rdev);
1932 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
1935 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1940 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1948 static void ci_program_display_gap(struct radeon_device *rdev)
1953 u32 ref_clock = rdev->clock.spll.reference_freq;
1954 u32 refresh_rate = r600_dpm_get_vrefresh(rdev);
1955 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
1958 if (rdev->pm.dpm.new_active_crtc_count > 0)
1974 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
1975 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
1978 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1));
1982 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
1984 struct ci_power_info *pi = ci_get_pi(rdev);
2004 static void ci_program_sstp(struct radeon_device *rdev)
2009 static void ci_enable_display_gap(struct radeon_device *rdev)
2020 static void ci_program_vc(struct radeon_device *rdev)
2038 static void ci_clear_vc(struct radeon_device *rdev)
2056 static int ci_upload_firmware(struct radeon_device *rdev)
2058 struct ci_power_info *pi = ci_get_pi(rdev);
2061 for (i = 0; i < rdev->usec_timeout; i++) {
2067 ci_stop_smc_clock(rdev);
2068 ci_reset_smc(rdev);
2070 return ci_load_smc_ucode(rdev, pi->sram_end);
2074 static int ci_get_svi2_voltage_table(struct radeon_device *rdev,
2095 static int ci_construct_voltage_tables(struct radeon_device *rdev)
2097 struct ci_power_info *pi = ci_get_pi(rdev);
2101 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
2107 ret = ci_get_svi2_voltage_table(rdev,
2108 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2115 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC,
2119 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
2125 ret = ci_get_svi2_voltage_table(rdev,
2126 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2133 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI,
2137 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
2143 ret = ci_get_svi2_voltage_table(rdev,
2144 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2151 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD,
2157 static void ci_populate_smc_voltage_table(struct radeon_device *rdev,
2163 ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
2179 static int ci_populate_smc_vddc_table(struct radeon_device *rdev,
2182 struct ci_power_info *pi = ci_get_pi(rdev);
2187 ci_populate_smc_voltage_table(rdev,
2202 static int ci_populate_smc_vddci_table(struct radeon_device *rdev,
2206 struct ci_power_info *pi = ci_get_pi(rdev);
2210 ci_populate_smc_voltage_table(rdev,
2225 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev,
2228 struct ci_power_info *pi = ci_get_pi(rdev);
2233 ci_populate_smc_voltage_table(rdev,
2248 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev,
2253 ret = ci_populate_smc_vddc_table(rdev, table);
2257 ret = ci_populate_smc_vddci_table(rdev, table);
2261 ret = ci_populate_smc_mvdd_table(rdev, table);
2268 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
2271 struct ci_power_info *pi = ci_get_pi(rdev);
2275 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
2276 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
2282 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
2289 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
2298 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
2301 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
2302 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2304 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2306 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
2309 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2311 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2313 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2319 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2321 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2323 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
2326 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2328 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2330 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2340 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev,
2357 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev,
2374 static int ci_init_arb_table_index(struct radeon_device *rdev)
2376 struct ci_power_info *pi = ci_get_pi(rdev);
2380 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
2388 return ci_write_smc_sram_dword(rdev, pi->arb_table_start,
2392 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev,
2413 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
2433 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
2435 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2438 static int ci_reset_to_default(struct radeon_device *rdev)
2440 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2444 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev)
2453 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2456 static void ci_register_patching_mc_arb(struct radeon_device *rdev,
2468 ((rdev->pdev->device == 0x67B0) ||
2469 (rdev->pdev->device == 0x67B1))) {
2483 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev,
2492 radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2498 ci_register_patching_mc_arb(rdev, sclk, mclk, &dram_timing2);
2507 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev)
2509 struct ci_power_info *pi = ci_get_pi(rdev);
2518 ret = ci_populate_memory_timing_parameters(rdev,
2528 ret = ci_copy_bytes_to_smc(rdev,
2537 static int ci_program_memory_timing_parameters(struct radeon_device *rdev)
2539 struct ci_power_info *pi = ci_get_pi(rdev);
2544 return ci_do_program_memory_timing_parameters(rdev);
2547 static void ci_populate_smc_initial_state(struct radeon_device *rdev,
2551 struct ci_power_info *pi = ci_get_pi(rdev);
2554 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2555 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2562 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2563 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2587 static void ci_populate_smc_link_level(struct radeon_device *rdev,
2590 struct ci_power_info *pi = ci_get_pi(rdev);
2609 static int ci_populate_smc_uvd_level(struct radeon_device *rdev,
2617 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2621 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2623 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2625 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2628 ret = radeon_atom_get_clock_dividers(rdev,
2636 ret = radeon_atom_get_clock_dividers(rdev,
2652 static int ci_populate_smc_vce_level(struct radeon_device *rdev,
2660 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2664 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2666 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2669 ret = radeon_atom_get_clock_dividers(rdev,
2685 static int ci_populate_smc_acp_level(struct radeon_device *rdev,
2693 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2697 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2699 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2702 ret = radeon_atom_get_clock_dividers(rdev,
2717 static int ci_populate_smc_samu_level(struct radeon_device *rdev,
2725 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2729 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2731 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2734 ret = radeon_atom_get_clock_dividers(rdev,
2749 static int ci_calculate_mclk_params(struct radeon_device *rdev,
2755 struct ci_power_info *pi = ci_get_pi(rdev);
2768 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2792 u32 reference_clock = rdev->clock.mpll.reference_freq;
2801 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2836 static int ci_populate_single_memory_level(struct radeon_device *rdev,
2840 struct ci_power_info *pi = ci_get_pi(rdev);
2844 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2845 ret = ci_get_dependency_volt_by_clk(rdev,
2846 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2852 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2853 ret = ci_get_dependency_volt_by_clk(rdev,
2854 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2860 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
2861 ret = ci_get_dependency_volt_by_clk(rdev,
2862 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2871 ci_populate_phase_value_based_on_mclk(rdev,
2872 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2894 (rdev->pm.dpm.new_active_crtc_count <= 2))
2926 ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
2950 static int ci_populate_smc_acpi_level(struct radeon_device *rdev,
2953 struct ci_power_info *pi = ci_get_pi(rdev);
2971 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
2973 ret = radeon_atom_get_clock_dividers(rdev,
3022 if (ci_populate_mvdd_value(rdev, 0, &voltage_level))
3066 static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
3068 struct ci_power_info *pi = ci_get_pi(rdev);
3073 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
3076 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
3083 static int ci_populate_ulv_level(struct radeon_device *rdev,
3086 struct ci_power_info *pi = ci_get_pi(rdev);
3087 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time;
3098 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3102 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
3104 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3108 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
3120 static int ci_calculate_sclk_params(struct radeon_device *rdev,
3124 struct ci_power_info *pi = ci_get_pi(rdev);
3130 u32 reference_clock = rdev->clock.spll.reference_freq;
3135 ret = radeon_atom_get_clock_dividers(rdev,
3152 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
3176 static int ci_populate_single_graphic_level(struct radeon_device *rdev,
3181 struct ci_power_info *pi = ci_get_pi(rdev);
3184 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
3188 ret = ci_get_dependency_volt_by_clk(rdev,
3189 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3200 ci_populate_phase_value_based_on_sclk(rdev,
3201 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
3216 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev,
3237 static int ci_populate_all_graphic_levels(struct radeon_device *rdev)
3239 struct ci_power_info *pi = ci_get_pi(rdev);
3251 ret = ci_populate_single_graphic_level(rdev,
3269 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
3278 static int ci_populate_ulv_state(struct radeon_device *rdev,
3281 return ci_populate_ulv_level(rdev, ulv_level);
3284 static int ci_populate_all_memory_levels(struct radeon_device *rdev)
3286 struct ci_power_info *pi = ci_get_pi(rdev);
3300 ret = ci_populate_single_memory_level(rdev,
3310 ((rdev->pdev->device == 0x67B0) || (rdev->pdev->device == 0x67B1))) {
3326 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
3335 static void ci_reset_single_dpm_table(struct radeon_device *rdev,
3354 static int ci_setup_default_pcie_tables(struct radeon_device *rdev)
3356 struct ci_power_info *pi = ci_get_pi(rdev);
3369 ci_reset_single_dpm_table(rdev,
3373 if (rdev->family == CHIP_BONAIRE)
3402 static int ci_setup_default_dpm_tables(struct radeon_device *rdev)
3404 struct ci_power_info *pi = ci_get_pi(rdev);
3406 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3408 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
3410 &rdev->pm.dpm.dyn_state.cac_leakage_table;
3424 ci_reset_single_dpm_table(rdev,
3427 ci_reset_single_dpm_table(rdev,
3430 ci_reset_single_dpm_table(rdev,
3433 ci_reset_single_dpm_table(rdev,
3436 ci_reset_single_dpm_table(rdev,
3475 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3485 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3495 ci_setup_default_pcie_tables(rdev);
3516 static int ci_init_smc_table(struct radeon_device *rdev)
3518 struct ci_power_info *pi = ci_get_pi(rdev);
3520 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
3524 ret = ci_setup_default_dpm_tables(rdev);
3529 ci_populate_smc_voltage_tables(rdev, table);
3531 ci_init_fps_limits(rdev);
3533 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3536 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3543 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);
3549 ret = ci_populate_all_graphic_levels(rdev);
3553 ret = ci_populate_all_memory_levels(rdev);
3557 ci_populate_smc_link_level(rdev, table);
3559 ret = ci_populate_smc_acpi_level(rdev, table);
3563 ret = ci_populate_smc_vce_level(rdev, table);
3567 ret = ci_populate_smc_acp_level(rdev, table);
3571 ret = ci_populate_smc_samu_level(rdev, table);
3575 ret = ci_do_program_memory_timing_parameters(rdev);
3579 ret = ci_populate_smc_uvd_level(rdev, table);
3602 ci_populate_smc_initial_state(rdev, radeon_boot_state);
3604 ret = ci_populate_bapm_parameters_in_dpm_table(rdev);
3652 ret = ci_copy_bytes_to_smc(rdev,
3664 static void ci_trim_single_dpm_states(struct radeon_device *rdev,
3679 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev,
3683 struct ci_power_info *pi = ci_get_pi(rdev);
3710 static int ci_trim_dpm_states(struct radeon_device *rdev,
3714 struct ci_power_info *pi = ci_get_pi(rdev);
3725 ci_trim_single_dpm_states(rdev,
3730 ci_trim_single_dpm_states(rdev,
3735 ci_trim_pcie_dpm_states(rdev,
3744 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev)
3747 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3749 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3759 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3766 return (ci_send_msg_to_smc_with_parameter(rdev,
3776 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
3778 struct ci_power_info *pi = ci_get_pi(rdev);
3781 ci_apply_disp_minimum_voltage_request(rdev);
3785 result = ci_send_msg_to_smc_with_parameter(rdev,
3795 result = ci_send_msg_to_smc_with_parameter(rdev,
3805 result = ci_send_msg_to_smc_with_parameter(rdev,
3816 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev,
3819 struct ci_power_info *pi = ci_get_pi(rdev);
3853 if (rdev->pm.dpm.current_active_crtc_count !=
3854 rdev->pm.dpm.new_active_crtc_count)
3858 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev,
3861 struct ci_power_info *pi = ci_get_pi(rdev);
3878 ret = ci_populate_all_graphic_levels(rdev);
3884 ret = ci_populate_all_memory_levels(rdev);
3892 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
3894 struct ci_power_info *pi = ci_get_pi(rdev);
3898 if (rdev->pm.dpm.ac_power)
3899 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3901 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3906 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3907 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3915 ci_send_msg_to_smc_with_parameter(rdev,
3922 ci_send_msg_to_smc_with_parameter(rdev,
3930 ci_send_msg_to_smc_with_parameter(rdev,
3936 return (ci_send_msg_to_smc(rdev, enable ?
3941 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
3943 struct ci_power_info *pi = ci_get_pi(rdev);
3947 if (rdev->pm.dpm.ac_power)
3948 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3950 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3954 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3955 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3963 ci_send_msg_to_smc_with_parameter(rdev,
3968 return (ci_send_msg_to_smc(rdev, enable ?
3974 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
3976 struct ci_power_info *pi = ci_get_pi(rdev);
3980 if (rdev->pm.dpm.ac_power)
3981 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3983 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3987 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3988 if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3996 ci_send_msg_to_smc_with_parameter(rdev,
4000 return (ci_send_msg_to_smc(rdev, enable ?
4005 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
4007 struct ci_power_info *pi = ci_get_pi(rdev);
4011 if (rdev->pm.dpm.ac_power)
4012 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4014 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4018 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4019 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4027 ci_send_msg_to_smc_with_parameter(rdev,
4032 return (ci_send_msg_to_smc(rdev, enable ?
4038 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
4040 struct ci_power_info *pi = ci_get_pi(rdev);
4045 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
4049 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
4057 return ci_enable_uvd_dpm(rdev, !gate);
4060 static u8 ci_get_vce_boot_level(struct radeon_device *rdev)
4065 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
4075 static int ci_update_vce_dpm(struct radeon_device *rdev,
4079 struct ci_power_info *pi = ci_get_pi(rdev);
4086 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
4088 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
4094 ret = ci_enable_vce_dpm(rdev, true);
4097 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);
4099 ret = ci_enable_vce_dpm(rdev, false);
4106 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
4108 return ci_enable_samu_dpm(rdev, gate);
4111 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
4113 struct ci_power_info *pi = ci_get_pi(rdev);
4125 return ci_enable_acp_dpm(rdev, !gate);
4129 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev,
4132 struct ci_power_info *pi = ci_get_pi(rdev);
4135 ret = ci_trim_dpm_states(rdev, radeon_state);
4155 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,
4167 int ci_dpm_force_performance_level(struct radeon_device *rdev,
4170 struct ci_power_info *pi = ci_get_pi(rdev);
4182 ret = ci_dpm_force_state_pcie(rdev, level);
4185 for (i = 0; i < rdev->usec_timeout; i++) {
4201 ret = ci_dpm_force_state_sclk(rdev, levels);
4204 for (i = 0; i < rdev->usec_timeout; i++) {
4220 ret = ci_dpm_force_state_mclk(rdev, levels);
4223 for (i = 0; i < rdev->usec_timeout; i++) {
4235 levels = ci_get_lowest_enabled_level(rdev,
4237 ret = ci_dpm_force_state_sclk(rdev, levels);
4240 for (i = 0; i < rdev->usec_timeout; i++) {
4250 levels = ci_get_lowest_enabled_level(rdev,
4252 ret = ci_dpm_force_state_mclk(rdev, levels);
4255 for (i = 0; i < rdev->usec_timeout; i++) {
4265 levels = ci_get_lowest_enabled_level(rdev,
4267 ret = ci_dpm_force_state_pcie(rdev, levels);
4270 for (i = 0; i < rdev->usec_timeout; i++) {
4282 smc_result = ci_send_msg_to_smc(rdev,
4287 ret = ci_upload_dpm_level_enable_mask(rdev);
4292 rdev->pm.dpm.forced_level = level;
4297 static int ci_set_mc_special_registers(struct radeon_device *rdev,
4300 struct ci_power_info *pi = ci_get_pi(rdev);
4495 static int ci_register_patching_mc_seq(struct radeon_device *rdev,
4506 ((rdev->pdev->device == 0x67B0) ||
4507 (rdev->pdev->device == 0x67B1))) {
4585 static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
4587 struct ci_power_info *pi = ci_get_pi(rdev);
4590 u8 module_index = rv770_get_memory_module_index(rdev);
4618 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4628 ret = ci_register_patching_mc_seq(rdev, ci_table);
4632 ret = ci_set_mc_special_registers(rdev, ci_table);
4644 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev,
4647 struct ci_power_info *pi = ci_get_pi(rdev);
4679 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
4683 struct ci_power_info *pi = ci_get_pi(rdev);
4699 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
4702 struct ci_power_info *pi = ci_get_pi(rdev);
4706 ci_convert_mc_reg_table_entry_to_smc(rdev,
4711 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev)
4713 struct ci_power_info *pi = ci_get_pi(rdev);
4718 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);
4721 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4723 return ci_copy_bytes_to_smc(rdev,
4730 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev)
4732 struct ci_power_info *pi = ci_get_pi(rdev);
4739 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4741 return ci_copy_bytes_to_smc(rdev,
4750 static void ci_enable_voltage_control(struct radeon_device *rdev)
4758 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev,
4774 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev)
4784 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev)
4810 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev,
4814 struct ci_power_info *pi = ci_get_pi(rdev);
4816 ci_get_maximum_link_speed(rdev, radeon_new_state);
4820 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state);
4830 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4837 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4842 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev);
4851 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
4855 struct ci_power_info *pi = ci_get_pi(rdev);
4857 ci_get_maximum_link_speed(rdev, radeon_new_state);
4869 (ci_get_current_pcie_speed(rdev) > 0))
4873 radeon_acpi_pcie_performance_request(rdev, request, false);
4878 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev)
4880 struct ci_power_info *pi = ci_get_pi(rdev);
4882 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
4884 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
4886 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
4909 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
4911 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
4913 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
4915 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
4921 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc)
4923 struct ci_power_info *pi = ci_get_pi(rdev);
4935 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci)
4937 struct ci_power_info *pi = ci_get_pi(rdev);
4949 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4956 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4960 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev,
4967 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
4971 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4978 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4982 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4989 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4993 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev,
5000 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
5004 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev,
5008 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);
5009 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);
5013 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev,
5020 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);
5024 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev)
5027 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5028 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5029 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5030 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5031 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5032 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
5033 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev,
5034 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5035 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5036 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
5037 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5038 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
5039 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5040 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
5041 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5042 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
5043 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev,
5044 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table);
5045 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
5046 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
5047 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
5048 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
5049 ci_patch_cac_leakage_table_with_vddc_leakage(rdev,
5050 &rdev->pm.dpm.dyn_state.cac_leakage_table);
5054 static void ci_get_memory_type(struct radeon_device *rdev)
5056 struct ci_power_info *pi = ci_get_pi(rdev);
5069 static void ci_update_current_ps(struct radeon_device *rdev,
5073 struct ci_power_info *pi = ci_get_pi(rdev);
5080 static void ci_update_requested_ps(struct radeon_device *rdev,
5084 struct ci_power_info *pi = ci_get_pi(rdev);
5091 int ci_dpm_pre_set_power_state(struct radeon_device *rdev)
5093 struct ci_power_info *pi = ci_get_pi(rdev);
5094 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
5097 ci_update_requested_ps(rdev, new_ps);
5099 ci_apply_state_adjust_rules(rdev, &pi->requested_rps);
5104 void ci_dpm_post_set_power_state(struct radeon_device *rdev)
5106 struct ci_power_info *pi = ci_get_pi(rdev);
5109 ci_update_current_ps(rdev, new_ps);
5113 void ci_dpm_setup_asic(struct radeon_device *rdev)
5117 r = ci_mc_load_microcode(rdev);
5120 ci_read_clock_registers(rdev);
5121 ci_get_memory_type(rdev);
5122 ci_enable_acpi_power_management(rdev);
5123 ci_init_sclk_t(rdev);
5126 int ci_dpm_enable(struct radeon_device *rdev)
5128 struct ci_power_info *pi = ci_get_pi(rdev);
5129 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5132 if (ci_is_smc_running(rdev))
5135 ci_enable_voltage_control(rdev);
5136 ret = ci_construct_voltage_tables(rdev);
5143 ret = ci_initialize_mc_reg_table(rdev);
5148 ci_enable_spread_spectrum(rdev, true);
5150 ci_enable_thermal_protection(rdev, true);
5151 ci_program_sstp(rdev);
5152 ci_enable_display_gap(rdev);
5153 ci_program_vc(rdev);
5154 ret = ci_upload_firmware(rdev);
5159 ret = ci_process_firmware_header(rdev);
5164 ret = ci_initial_switch_from_arb_f0_to_f1(rdev);
5169 ret = ci_init_smc_table(rdev);
5174 ret = ci_init_arb_table_index(rdev);
5180 ret = ci_populate_initial_mc_reg_table(rdev);
5186 ret = ci_populate_pm_base(rdev);
5191 ci_dpm_start_smc(rdev);
5192 ci_enable_vr_hot_gpio_interrupt(rdev);
5193 ret = ci_notify_smc_display_change(rdev, false);
5198 ci_enable_sclk_control(rdev, true);
5199 ret = ci_enable_ulv(rdev, true);
5204 ret = ci_enable_ds_master_switch(rdev, true);
5209 ret = ci_start_dpm(rdev);
5214 ret = ci_enable_didt(rdev, true);
5219 ret = ci_enable_smc_cac(rdev, true);
5224 ret = ci_enable_power_containment(rdev, true);
5230 ret = ci_power_control_set_level(rdev);
5236 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5238 ret = ci_enable_thermal_based_sclk_dpm(rdev, true);
5244 ci_thermal_start_thermal_controller(rdev);
5246 ci_update_current_ps(rdev, boot_ps);
5251 static int ci_set_temperature_range(struct radeon_device *rdev)
5255 ret = ci_thermal_enable_alert(rdev, false);
5258 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
5261 ret = ci_thermal_enable_alert(rdev, true);
5268 int ci_dpm_late_enable(struct radeon_device *rdev)
5272 ret = ci_set_temperature_range(rdev);
5276 ci_dpm_powergate_uvd(rdev, true);
5281 void ci_dpm_disable(struct radeon_device *rdev)
5283 struct ci_power_info *pi = ci_get_pi(rdev);
5284 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5286 ci_dpm_powergate_uvd(rdev, false);
5288 if (!ci_is_smc_running(rdev))
5291 ci_thermal_stop_thermal_controller(rdev);
5294 ci_enable_thermal_protection(rdev, false);
5295 ci_enable_power_containment(rdev, false);
5296 ci_enable_smc_cac(rdev, false);
5297 ci_enable_didt(rdev, false);
5298 ci_enable_spread_spectrum(rdev, false);
5299 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5300 ci_stop_dpm(rdev);
5301 ci_enable_ds_master_switch(rdev, false);
5302 ci_enable_ulv(rdev, false);
5303 ci_clear_vc(rdev);
5304 ci_reset_to_default(rdev);
5305 ci_dpm_stop_smc(rdev);
5306 ci_force_switch_to_arb_f0(rdev);
5307 ci_enable_thermal_based_sclk_dpm(rdev, false);
5309 ci_update_current_ps(rdev, boot_ps);
5312 int ci_dpm_set_power_state(struct radeon_device *rdev)
5314 struct ci_power_info *pi = ci_get_pi(rdev);
5319 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
5321 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
5322 ret = ci_freeze_sclk_mclk_dpm(rdev);
5327 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps);
5332 ret = ci_generate_dpm_level_enable_mask(rdev, new_ps);
5338 ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
5344 ret = ci_update_sclk_t(rdev);
5350 ret = ci_update_and_upload_mc_reg_table(rdev);
5356 ret = ci_program_memory_timing_parameters(rdev);
5361 ret = ci_unfreeze_sclk_mclk_dpm(rdev);
5366 ret = ci_upload_dpm_level_enable_mask(rdev);
5372 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
5378 void ci_dpm_reset_asic(struct radeon_device *rdev)
5380 ci_set_boot_state(rdev);
5384 void ci_dpm_display_configuration_changed(struct radeon_device *rdev)
5386 ci_program_display_gap(rdev);
5412 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev,
5430 rdev->pm.dpm.boot_ps = rps;
5432 rdev->pm.dpm.uvd_ps = rps;
5435 static void ci_parse_pplib_clock_info(struct radeon_device *rdev,
5439 struct ci_power_info *pi = ci_get_pi(rdev);
5450 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
5454 pl->pcie_lane = r600_get_pcie_lane_support(rdev,
5504 static int ci_parse_power_table(struct radeon_device *rdev)
5506 struct radeon_mode_info *mode_info = &rdev->mode_info;
5537 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
5540 if (!rdev->pm.dpm.ps)
5543 rdev->pm.dpm.num_ps = 0;
5550 if (!rdev->pm.power_state[i].clock_info) {
5559 rdev->pm.dpm.ps[i].ps_priv = ps;
5560 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
5574 ci_parse_pplib_clock_info(rdev,
5575 &rdev->pm.dpm.ps[i], k,
5580 rdev->pm.dpm.num_ps = i + 1;
5586 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
5593 rdev->pm.dpm.vce_states[i].sclk = sclk;
5594 rdev->pm.dpm.vce_states[i].mclk = mclk;
5600 for (i = 0; i < rdev->pm.dpm.num_ps; i++)
5601 kfree(rdev->pm.dpm.ps[i].ps_priv);
5602 kfree(rdev->pm.dpm.ps);
5606 static int ci_get_vbios_boot_values(struct radeon_device *rdev,
5609 struct radeon_mode_info *mode_info = &rdev->mode_info;
5623 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev);
5624 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev);
5633 void ci_dpm_fini(struct radeon_device *rdev)
5637 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
5638 kfree(rdev->pm.dpm.ps[i].ps_priv);
5640 kfree(rdev->pm.dpm.ps);
5641 kfree(rdev->pm.dpm.priv);
5642 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5643 r600_free_extended_power_table(rdev);
5646 int ci_dpm_init(struct radeon_device *rdev)
5655 struct pci_dev *root = rdev->pdev->bus->self;
5661 rdev->pm.dpm.priv = pi;
5663 if (!pci_is_root_bus(rdev->pdev->bus))
5690 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
5692 kfree(rdev->pm.dpm.priv);
5696 ret = r600_get_platform_caps(rdev);
5698 kfree(rdev->pm.dpm.priv);
5702 ret = r600_parse_extended_power_table(rdev);
5704 kfree(rdev->pm.dpm.priv);
5708 ret = ci_parse_power_table(rdev);
5710 kfree(rdev->pm.dpm.priv);
5711 r600_free_extended_power_table(rdev);
5735 if ((rdev->pdev->device == 0x6658) &&
5736 (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) {
5747 ci_initialize_powertune_defaults(rdev);
5756 ci_get_leakage_voltages(rdev);
5757 ci_patch_dependency_tables_with_leakage(rdev);
5758 ci_set_private_data_variables_based_on_pptable(rdev);
5760 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5764 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5765 ci_dpm_fini(rdev);
5768 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5769 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5770 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5771 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5772 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5773 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5774 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5775 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5776 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5778 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5779 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5780 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5782 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5783 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5784 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5785 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5787 if (rdev->family == CHIP_HAWAII) {
5801 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_VRHOT_GPIO_PINID);
5804 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5807 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5810 gpio = radeon_atombios_lookup_gpio(rdev, PP_AC_DC_SWITCH_GPIO_PINID);
5813 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5816 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5819 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_PCC_GPIO_PINID);
5851 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5853 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5856 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5857 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5859 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5862 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5865 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5866 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5868 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5871 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5878 radeon_acpi_is_pcie_performance_request_supported(rdev);
5883 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
5894 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
5904 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
5905 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
5906 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
5907 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
5914 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
5917 struct ci_power_info *pi = ci_get_pi(rdev);
5919 u32 sclk = ci_get_average_sclk_freq(rdev);
5920 u32 mclk = ci_get_average_mclk_freq(rdev);
5928 void ci_dpm_print_power_state(struct radeon_device *rdev,
5943 r600_dpm_print_ps_status(rdev, rps);
5946 u32 ci_dpm_get_current_sclk(struct radeon_device *rdev)
5948 u32 sclk = ci_get_average_sclk_freq(rdev);
5953 u32 ci_dpm_get_current_mclk(struct radeon_device *rdev)
5955 u32 mclk = ci_get_average_mclk_freq(rdev);
5960 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)
5962 struct ci_power_info *pi = ci_get_pi(rdev);
5971 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)
5973 struct ci_power_info *pi = ci_get_pi(rdev);