Lines Matching defs:rdev
53 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1226 static u32 btc_get_valid_mclk(struct radeon_device *rdev,
1229 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_mclk_values,
1233 static u32 btc_get_valid_sclk(struct radeon_device *rdev,
1236 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_sclk_values,
1240 void btc_skip_blacklist_clocks(struct radeon_device *rdev,
1259 *sclk = btc_get_valid_sclk(rdev, max_sclk, *sclk + 1);
1262 btc_skip_blacklist_clocks(rdev, max_sclk, max_mclk, sclk, mclk);
1267 void btc_adjust_clock_combinations(struct radeon_device *rdev,
1279 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio)
1280 pl->sclk = btc_get_valid_sclk(rdev,
1283 (rdev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
1284 rdev->pm.dpm.dyn_state.mclk_sclk_ratio);
1286 if ((pl->sclk - pl->mclk) > rdev->pm.dpm.dyn_state.sclk_mclk_delta)
1287 pl->mclk = btc_get_valid_mclk(rdev,
1290 rdev->pm.dpm.dyn_state.sclk_mclk_delta);
1306 void btc_apply_voltage_delta_rules(struct radeon_device *rdev,
1310 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1317 if ((*vddc - *vddci) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) {
1319 (*vddc - rdev->pm.dpm.dyn_state.vddc_vddci_delta));
1323 if ((*vddci - *vddc) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) {
1325 (*vddci - rdev->pm.dpm.dyn_state.vddc_vddci_delta));
1331 static void btc_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
1334 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1373 static void btc_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
1376 btc_enable_bif_dynamic_pcie_gen2(rdev, enable);
1384 static int btc_disable_ulv(struct radeon_device *rdev)
1386 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1389 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) != PPSMC_Result_OK)
1395 static int btc_populate_ulv_state(struct radeon_device *rdev,
1399 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1403 ret = cypress_convert_power_level_to_smc(rdev,
1424 static int btc_populate_smc_acpi_state(struct radeon_device *rdev,
1427 int ret = cypress_populate_smc_acpi_state(rdev, table);
1438 void btc_program_mgcg_hw_sequence(struct radeon_device *rdev,
1452 static void btc_cg_clock_gating_default(struct radeon_device *rdev)
1457 if (rdev->family == CHIP_BARTS) {
1460 } else if (rdev->family == CHIP_TURKS) {
1463 } else if (rdev->family == CHIP_CAICOS) {
1469 btc_program_mgcg_hw_sequence(rdev, p, count);
1472 static void btc_cg_clock_gating_enable(struct radeon_device *rdev,
1479 if (rdev->family == CHIP_BARTS) {
1482 } else if (rdev->family == CHIP_TURKS) {
1485 } else if (rdev->family == CHIP_CAICOS) {
1491 if (rdev->family == CHIP_BARTS) {
1494 } else if (rdev->family == CHIP_TURKS) {
1497 } else if (rdev->family == CHIP_CAICOS) {
1504 btc_program_mgcg_hw_sequence(rdev, p, count);
1507 static void btc_mg_clock_gating_default(struct radeon_device *rdev)
1512 if (rdev->family == CHIP_BARTS) {
1515 } else if (rdev->family == CHIP_TURKS) {
1518 } else if (rdev->family == CHIP_CAICOS) {
1524 btc_program_mgcg_hw_sequence(rdev, p, count);
1527 static void btc_mg_clock_gating_enable(struct radeon_device *rdev,
1534 if (rdev->family == CHIP_BARTS) {
1537 } else if (rdev->family == CHIP_TURKS) {
1540 } else if (rdev->family == CHIP_CAICOS) {
1546 if (rdev->family == CHIP_BARTS) {
1549 } else if (rdev->family == CHIP_TURKS) {
1552 } else if (rdev->family == CHIP_CAICOS) {
1559 btc_program_mgcg_hw_sequence(rdev, p, count);
1562 static void btc_ls_clock_gating_default(struct radeon_device *rdev)
1567 if (rdev->family == CHIP_BARTS) {
1570 } else if (rdev->family == CHIP_TURKS) {
1573 } else if (rdev->family == CHIP_CAICOS) {
1579 btc_program_mgcg_hw_sequence(rdev, p, count);
1582 static void btc_ls_clock_gating_enable(struct radeon_device *rdev,
1589 if (rdev->family == CHIP_BARTS) {
1592 } else if (rdev->family == CHIP_TURKS) {
1595 } else if (rdev->family == CHIP_CAICOS) {
1601 if (rdev->family == CHIP_BARTS) {
1604 } else if (rdev->family == CHIP_TURKS) {
1607 } else if (rdev->family == CHIP_CAICOS) {
1614 btc_program_mgcg_hw_sequence(rdev, p, count);
1617 bool btc_dpm_enabled(struct radeon_device *rdev)
1619 if (rv770_is_smc_running(rdev))
1625 static int btc_init_smc_table(struct radeon_device *rdev,
1628 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1629 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1635 cypress_populate_smc_voltage_tables(rdev, table);
1637 switch (rdev->pm.int_thermal_type) {
1650 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
1653 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1656 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1662 ret = cypress_populate_smc_initial_state(rdev, radeon_boot_state, table);
1670 ret = btc_populate_smc_acpi_state(rdev, table);
1675 ret = btc_populate_ulv_state(rdev, table);
1682 return rv770_copy_bytes_to_smc(rdev,
1689 static void btc_set_at_for_uvd(struct radeon_device *rdev,
1692 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1693 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1713 void btc_notify_uvd_to_smc(struct radeon_device *rdev,
1716 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1719 rv770_write_smc_soft_register(rdev,
1723 rv770_write_smc_soft_register(rdev,
1729 int btc_reset_to_default(struct radeon_device *rdev)
1731 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) != PPSMC_Result_OK)
1737 static void btc_stop_smc(struct radeon_device *rdev)
1741 for (i = 0; i < rdev->usec_timeout; i++) {
1748 r7xx_stop_smc(rdev);
1751 void btc_read_arb_registers(struct radeon_device *rdev)
1753 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1764 static void btc_set_arb0_registers(struct radeon_device *rdev,
1781 static void btc_set_boot_state_timing(struct radeon_device *rdev)
1783 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1786 btc_set_arb0_registers(rdev, &eg_pi->bootup_arb_registers);
1789 static bool btc_is_state_ulv_compatible(struct radeon_device *rdev,
1793 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1808 static int btc_set_ulv_dram_timing(struct radeon_device *rdev)
1811 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1814 radeon_atom_set_engine_dram_timings(rdev,
1818 val = rv770_calculate_memory_refresh_rate(rdev, ulv_pl->sclk);
1821 val = cypress_calculate_burst_time(rdev, ulv_pl->sclk, ulv_pl->mclk);
1827 static int btc_enable_ulv(struct radeon_device *rdev)
1829 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) != PPSMC_Result_OK)
1835 static int btc_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
1839 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1842 if (btc_is_state_ulv_compatible(rdev, radeon_new_state)) {
1844 ret = btc_set_ulv_dram_timing(rdev);
1846 ret = btc_enable_ulv(rdev);
1914 static int btc_set_mc_special_registers(struct radeon_device *rdev,
1917 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2015 static int btc_initialize_mc_reg_table(struct radeon_device *rdev)
2019 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2021 u8 module_index = rv770_get_memory_module_index(rdev);
2040 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
2051 ret = btc_set_mc_special_registers(rdev, eg_table);
2064 static void btc_init_stutter_mode(struct radeon_device *rdev)
2066 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2080 bool btc_dpm_vblank_too_short(struct radeon_device *rdev)
2082 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2083 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
2093 static void btc_apply_state_adjust_rules(struct radeon_device *rdev,
2102 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
2103 btc_dpm_vblank_too_short(rdev))
2108 if (rdev->pm.dpm.ac_power)
2109 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2111 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
2113 if (rdev->pm.dpm.ac_power == false) {
2162 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
2198 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
2200 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
2203 btc_adjust_clock_combinations(rdev, max_limits, &ps->low);
2204 btc_adjust_clock_combinations(rdev, max_limits, &ps->medium);
2205 btc_adjust_clock_combinations(rdev, max_limits, &ps->high);
2207 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2209 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2211 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2213 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
2214 rdev->clock.current_dispclk, max_limits->vddc, &ps->low.vddc);
2216 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2218 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2220 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2222 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
2223 rdev->clock.current_dispclk, max_limits->vddc, &ps->medium.vddc);
2225 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2227 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2229 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2231 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
2232 rdev->clock.current_dispclk, max_limits->vddc, &ps->high.vddc);
2234 btc_apply_voltage_delta_rules(rdev, max_limits->vddc, max_limits->vddci,
2236 btc_apply_voltage_delta_rules(rdev, max_limits->vddc, max_limits->vddci,
2238 btc_apply_voltage_delta_rules(rdev, max_limits->vddc, max_limits->vddci,
2241 if ((ps->high.vddc <= rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) &&
2242 (ps->medium.vddc <= rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) &&
2243 (ps->low.vddc <= rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc))
2248 if (ps->low.vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2)
2250 if (ps->medium.vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2)
2252 if (ps->high.vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2)
2256 static void btc_update_current_ps(struct radeon_device *rdev,
2260 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2267 static void btc_update_requested_ps(struct radeon_device *rdev,
2271 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2279 void btc_dpm_reset_asic(struct radeon_device *rdev)
2281 rv770_restrict_performance_levels_before_switch(rdev);
2282 btc_disable_ulv(rdev);
2283 btc_set_boot_state_timing(rdev);
2284 rv770_set_boot_state(rdev);
2288 int btc_dpm_pre_set_power_state(struct radeon_device *rdev)
2290 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2291 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
2294 btc_update_requested_ps(rdev, new_ps);
2296 btc_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
2301 int btc_dpm_set_power_state(struct radeon_device *rdev)
2303 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2308 ret = btc_disable_ulv(rdev);
2309 btc_set_boot_state_timing(rdev);
2310 ret = rv770_restrict_performance_levels_before_switch(rdev);
2316 cypress_notify_link_speed_change_before_state_change(rdev, new_ps, old_ps);
2318 rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
2319 ret = rv770_halt_smc(rdev);
2324 btc_set_at_for_uvd(rdev, new_ps);
2326 btc_notify_uvd_to_smc(rdev, new_ps);
2327 ret = cypress_upload_sw_state(rdev, new_ps);
2333 ret = cypress_upload_mc_reg_table(rdev, new_ps);
2340 cypress_program_memory_timing_parameters(rdev, new_ps);
2342 ret = rv770_resume_smc(rdev);
2347 ret = rv770_set_sw_state(rdev);
2352 rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
2355 cypress_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
2357 ret = btc_set_power_state_conditionally_enable_ulv(rdev, new_ps);
2366 void btc_dpm_post_set_power_state(struct radeon_device *rdev)
2368 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2371 btc_update_current_ps(rdev, new_ps);
2374 int btc_dpm_enable(struct radeon_device *rdev)
2376 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2377 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2378 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
2382 btc_cg_clock_gating_default(rdev);
2384 if (btc_dpm_enabled(rdev))
2388 btc_mg_clock_gating_default(rdev);
2391 btc_ls_clock_gating_default(rdev);
2394 rv770_enable_voltage_control(rdev, true);
2395 ret = cypress_construct_voltage_tables(rdev);
2403 ret = cypress_get_mvdd_configuration(rdev);
2411 ret = btc_initialize_mc_reg_table(rdev);
2416 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
2417 rv770_enable_backbias(rdev, true);
2420 cypress_enable_spread_spectrum(rdev, true);
2423 rv770_enable_thermal_protection(rdev, true);
2425 rv770_setup_bsp(rdev);
2426 rv770_program_git(rdev);
2427 rv770_program_tp(rdev);
2428 rv770_program_tpp(rdev);
2429 rv770_program_sstp(rdev);
2430 rv770_program_engine_speed_parameters(rdev);
2431 cypress_enable_display_gap(rdev);
2432 rv770_program_vc(rdev);
2435 btc_enable_dynamic_pcie_gen2(rdev, true);
2437 ret = rv770_upload_firmware(rdev);
2442 ret = cypress_get_table_locations(rdev);
2447 ret = btc_init_smc_table(rdev, boot_ps);
2452 ret = cypress_populate_mc_reg_table(rdev, boot_ps);
2459 cypress_program_response_times(rdev);
2460 r7xx_start_smc(rdev);
2461 ret = cypress_notify_smc_display_change(rdev, false);
2466 cypress_enable_sclk_control(rdev, true);
2469 cypress_enable_mclk_control(rdev, true);
2471 cypress_start_dpm(rdev);
2474 btc_cg_clock_gating_enable(rdev, true);
2477 btc_mg_clock_gating_enable(rdev, true);
2480 btc_ls_clock_gating_enable(rdev, true);
2482 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
2484 btc_init_stutter_mode(rdev);
2486 btc_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
2491 void btc_dpm_disable(struct radeon_device *rdev)
2493 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2494 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2496 if (!btc_dpm_enabled(rdev))
2499 rv770_clear_vc(rdev);
2502 rv770_enable_thermal_protection(rdev, false);
2505 btc_enable_dynamic_pcie_gen2(rdev, false);
2507 if (rdev->irq.installed &&
2508 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
2509 rdev->irq.dpm_thermal = false;
2510 radeon_irq_set(rdev);
2514 btc_cg_clock_gating_enable(rdev, false);
2517 btc_mg_clock_gating_enable(rdev, false);
2520 btc_ls_clock_gating_enable(rdev, false);
2522 rv770_stop_dpm(rdev);
2523 btc_reset_to_default(rdev);
2524 btc_stop_smc(rdev);
2525 cypress_enable_spread_spectrum(rdev, false);
2527 btc_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
2530 void btc_dpm_setup_asic(struct radeon_device *rdev)
2532 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2535 r = ni_mc_load_microcode(rdev);
2538 rv770_get_memory_type(rdev);
2539 rv740_read_clock_registers(rdev);
2540 btc_read_arb_registers(rdev);
2541 rv770_read_voltage_smio_registers(rdev);
2544 cypress_advertise_gen2_capability(rdev);
2546 rv770_get_pcie_gen2_status(rdev);
2547 rv770_enable_acpi_pm(rdev);
2550 int btc_dpm_init(struct radeon_device *rdev)
2560 rdev->pm.dpm.priv = eg_pi;
2563 rv770_get_max_vddc(rdev);
2571 ret = r600_get_platform_caps(rdev);
2575 ret = rv7xx_parse_power_table(rdev);
2578 ret = r600_parse_extended_power_table(rdev);
2582 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
2586 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
2587 r600_free_extended_power_table(rdev);
2590 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
2591 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
2592 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
2593 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
2594 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 800;
2595 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
2596 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 800;
2597 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
2598 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 800;
2600 if (rdev->pm.dpm.voltage_response_time == 0)
2601 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
2602 if (rdev->pm.dpm.backbias_response_time == 0)
2603 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
2605 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2634 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0);
2637 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0);
2640 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0);
2642 rv770_get_engine_memory_ss(rdev);
2659 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
2666 if (rdev->flags & RADEON_IS_MOBILITY)
2680 radeon_acpi_is_pcie_performance_request_supported(rdev);
2685 if (rdev->family == CHIP_BARTS)
2691 if (ASIC_IS_LOMBOK(rdev))
2698 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
2699 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
2700 rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900;
2701 rdev->pm.dpm.dyn_state.valid_sclk_values.count = ARRAY_SIZE(btc_valid_sclk);
2702 rdev->pm.dpm.dyn_state.valid_sclk_values.values = btc_valid_sclk;
2703 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
2704 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
2706 if (rdev->family == CHIP_TURKS)
2707 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
2709 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 10000;
2712 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
2713 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
2714 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
2715 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2720 void btc_dpm_fini(struct radeon_device *rdev)
2724 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2725 kfree(rdev->pm.dpm.ps[i].ps_priv);
2727 kfree(rdev->pm.dpm.ps);
2728 kfree(rdev->pm.dpm.priv);
2729 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
2730 r600_free_extended_power_table(rdev);
2733 void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
2736 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2759 u32 btc_dpm_get_current_sclk(struct radeon_device *rdev)
2761 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2782 u32 btc_dpm_get_current_mclk(struct radeon_device *rdev)
2784 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2805 u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low)
2807 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2816 u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low)
2818 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);