Lines Matching refs:args
103 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
120 args.ucAction = ATOM_LCD_BLOFF;
121 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
123 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
124 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
125 args.ucAction = ATOM_LCD_BLON;
126 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
349 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
353 memset(&args, 0, sizeof(args));
366 args.ucAction = action;
369 args.ucDacStandard = ATOM_DAC1_PS2;
371 args.ucDacStandard = ATOM_DAC1_CV;
379 args.ucDacStandard = ATOM_DAC1_PAL;
385 args.ucDacStandard = ATOM_DAC1_NTSC;
389 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
391 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
401 TV_ENCODER_CONTROL_PS_ALLOCATION args;
405 memset(&args, 0, sizeof(args));
409 args.sTVEncoder.ucAction = action;
412 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
416 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
419 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
422 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
425 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
428 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
431 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
434 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
437 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
440 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
445 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
447 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
490 union dvo_encoder_control args;
494 memset(&args, 0, sizeof(args));
508 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
511 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
513 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
517 args.dvo.sDVOEncoder.ucAction = action;
518 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
520 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
523 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
527 args.dvo_v3.ucAction = action;
528 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
529 args.dvo_v3.ucDVOConfig = 0; /* XXX */
533 args.dvo_v4.ucAction = action;
534 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
535 args.dvo_v4.ucDVOConfig = 0; /* XXX */
536 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
548 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
563 union lvds_encoder_control args;
574 memset(&args, 0, sizeof(args));
600 args.v1.ucMisc = 0;
601 args.v1.ucAction = action;
603 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
604 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
607 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
609 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
612 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
614 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
616 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
621 args.v2.ucMisc = 0;
622 args.v2.ucAction = action;
625 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
628 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
629 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
630 args.v2.ucTruncate = 0;
631 args.v2.ucSpatial = 0;
632 args.v2.ucTemporal = 0;
633 args.v2.ucFRC = 0;
636 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
638 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
640 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
643 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
645 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
647 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
651 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
653 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
666 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
837 union dig_encoder_control args;
858 memset(&args, 0, sizeof(args));
876 args.v1.ucAction = action;
877 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
879 args.v3.ucPanelMode = panel_mode;
881 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
883 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
884 args.v1.ucLaneNum = dp_lane_count;
886 args.v1.ucLaneNum = 8;
888 args.v1.ucLaneNum = 4;
892 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
896 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
899 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
903 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
905 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
907 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
908 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
913 args.v3.ucAction = action;
914 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
916 args.v3.ucPanelMode = panel_mode;
918 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
920 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
921 args.v3.ucLaneNum = dp_lane_count;
923 args.v3.ucLaneNum = 8;
925 args.v3.ucLaneNum = 4;
927 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
928 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
930 args.v3.acConfig.ucDigSel = enc_override;
932 args.v3.acConfig.ucDigSel = dig->dig_encoder;
933 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
936 args.v4.ucAction = action;
937 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
939 args.v4.ucPanelMode = panel_mode;
941 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
943 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
944 args.v4.ucLaneNum = dp_lane_count;
946 args.v4.ucLaneNum = 8;
948 args.v4.ucLaneNum = 4;
950 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
952 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
954 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
956 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
958 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
962 args.v4.acConfig.ucDigSel = enc_override;
964 args.v4.acConfig.ucDigSel = dig->dig_encoder;
965 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
967 args.v4.ucHPD_ID = 0;
969 args.v4.ucHPD_ID = hpd_id + 1;
981 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1007 union dig_transmitter_control args;
1053 memset(&args, 0, sizeof(args));
1077 args.v1.ucAction = action;
1079 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1081 args.v1.asMode.ucLaneSel = lane_num;
1082 args.v1.asMode.ucLaneSet = lane_set;
1085 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1087 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1089 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1092 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1095 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1097 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1104 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1106 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1108 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1110 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1113 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1115 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1120 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1122 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1125 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1128 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1130 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1134 args.v2.ucAction = action;
1136 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1138 args.v2.asMode.ucLaneSel = lane_num;
1139 args.v2.asMode.ucLaneSet = lane_set;
1142 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1144 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1146 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1149 args.v2.acConfig.ucEncoderSel = dig_encoder;
1151 args.v2.acConfig.ucLinkSel = 1;
1155 args.v2.acConfig.ucTransmitterSel = 0;
1158 args.v2.acConfig.ucTransmitterSel = 1;
1161 args.v2.acConfig.ucTransmitterSel = 2;
1166 args.v2.acConfig.fCoherentMode = 1;
1167 args.v2.acConfig.fDPConnector = 1;
1170 args.v2.acConfig.fCoherentMode = 1;
1172 args.v2.acConfig.fDualLinkConnector = 1;
1176 args.v3.ucAction = action;
1178 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1180 args.v3.asMode.ucLaneSel = lane_num;
1181 args.v3.asMode.ucLaneSet = lane_set;
1184 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1186 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1188 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1192 args.v3.ucLaneNum = dp_lane_count;
1194 args.v3.ucLaneNum = 8;
1196 args.v3.ucLaneNum = 4;
1199 args.v3.acConfig.ucLinkSel = 1;
1201 args.v3.acConfig.ucEncoderSel = 1;
1209 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1211 args.v3.acConfig.ucRefClkSource = pll_id;
1215 args.v3.acConfig.ucTransmitterSel = 0;
1218 args.v3.acConfig.ucTransmitterSel = 1;
1221 args.v3.acConfig.ucTransmitterSel = 2;
1226 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1229 args.v3.acConfig.fCoherentMode = 1;
1231 args.v3.acConfig.fDualLinkConnector = 1;
1235 args.v4.ucAction = action;
1237 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1239 args.v4.asMode.ucLaneSel = lane_num;
1240 args.v4.asMode.ucLaneSet = lane_set;
1243 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1245 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1247 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1251 args.v4.ucLaneNum = dp_lane_count;
1253 args.v4.ucLaneNum = 8;
1255 args.v4.ucLaneNum = 4;
1258 args.v4.acConfig.ucLinkSel = 1;
1260 args.v4.acConfig.ucEncoderSel = 1;
1269 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1271 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1273 args.v4.acConfig.ucRefClkSource = pll_id;
1277 args.v4.acConfig.ucTransmitterSel = 0;
1280 args.v4.acConfig.ucTransmitterSel = 1;
1283 args.v4.acConfig.ucTransmitterSel = 2;
1288 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1291 args.v4.acConfig.fCoherentMode = 1;
1293 args.v4.acConfig.fDualLinkConnector = 1;
1297 args.v5.ucAction = action;
1299 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1301 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1306 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1308 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1312 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1314 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1318 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1320 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1323 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1327 args.v5.ucLaneNum = dp_lane_count;
1329 args.v5.ucLaneNum = 8;
1331 args.v5.ucLaneNum = 4;
1332 args.v5.ucConnObjId = connector_object_id;
1333 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1336 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1338 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1341 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1344 args.v5.asConfig.ucCoherentMode = 1;
1347 args.v5.asConfig.ucHPDSel = 0;
1349 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1350 args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder);
1351 args.v5.ucDPLaneSet = lane_set;
1363 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1378 union dig_transmitter_control args;
1395 memset(&args, 0, sizeof(args));
1397 args.v1.ucAction = action;
1399 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1430 union external_encoder_control args;
1455 memset(&args, 0, sizeof(args));
1468 args.v1.sDigEncoder.ucAction = action;
1469 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1470 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1472 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1474 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1475 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1477 args.v1.sDigEncoder.ucLaneNum = 8;
1479 args.v1.sDigEncoder.ucLaneNum = 4;
1482 args.v3.sExtEncoder.ucAction = action;
1484 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1486 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1487 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1489 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1491 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1493 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1494 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1496 args.v3.sExtEncoder.ucLaneNum = 8;
1498 args.v3.sExtEncoder.ucLaneNum = 4;
1501 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1504 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1507 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1510 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1521 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1531 ENABLE_YUV_PS_ALLOCATION args;
1535 memset(&args, 0, sizeof(args));
1553 args.ucEnable = ATOM_ENABLE;
1554 args.ucCRTC = radeon_crtc->crtc_id;
1556 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1567 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1570 memset(&args, 0, sizeof(args));
1615 args.ucAction = ATOM_ENABLE;
1620 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1623 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1630 args.ucAction = ATOM_LCD_BLON;
1631 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1638 args.ucAction = ATOM_DISABLE;
1639 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1641 args.ucAction = ATOM_LCD_BLOFF;
1642 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1850 union crtc_source_param args;
1855 memset(&args, 0, sizeof(args));
1866 args.v1.ucCRTC = radeon_crtc->crtc_id;
1869 args.v1.ucCRTC = radeon_crtc->crtc_id;
1871 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1876 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1881 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1883 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1888 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1893 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1895 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1897 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1902 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1904 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1906 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1911 args.v2.ucCRTC = radeon_crtc->crtc_id;
1916 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1918 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1920 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1922 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1924 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1935 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1938 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1941 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1944 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1947 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1950 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1953 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1958 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1962 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1964 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1966 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1970 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1972 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1974 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1985 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2282 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2286 memset(&args, 0, sizeof(args));
2291 args.sDacload.ucMisc = 0;
2295 args.sDacload.ucDacType = ATOM_DAC_A;
2297 args.sDacload.ucDacType = ATOM_DAC_B;
2300 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2302 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2304 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2306 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2308 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2310 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2313 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);