Lines Matching defs:rdev
43 struct radeon_device *rdev = dev->dev_private;
80 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
86 struct radeon_device *rdev = dev->dev_private;
96 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
153 if (ASIC_IS_AVIVO(rdev))
160 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
162 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
163 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
171 struct radeon_device *rdev = dev->dev_private;
181 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
188 struct radeon_device *rdev = dev->dev_private;
197 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
204 struct radeon_device *rdev = dev->dev_private;
213 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
230 struct radeon_device *rdev = dev->dev_private;
237 if (ASIC_IS_DCE8(rdev)) {
245 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
247 if (ASIC_IS_DCE8(rdev))
255 struct radeon_device *rdev = dev->dev_private;
264 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
270 struct radeon_device *rdev = dev->dev_private;
277 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
291 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
298 radeon_pm_compute_clocks(rdev);
307 struct radeon_device *rdev = dev->dev_private;
346 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
354 struct radeon_device *rdev = dev->dev_private;
392 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
395 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
399 if (ASIC_IS_DCE4(rdev)) {
415 } else if (ASIC_IS_AVIVO(rdev)) {
443 static void atombios_crtc_program_ss(struct radeon_device *rdev,
464 for (i = 0; i < rdev->num_crtc; i++) {
465 if (rdev->mode_info.crtcs[i] &&
466 rdev->mode_info.crtcs[i]->enabled &&
468 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
480 if (ASIC_IS_DCE5(rdev)) {
499 } else if (ASIC_IS_DCE4(rdev)) {
518 } else if (ASIC_IS_DCE3(rdev)) {
526 } else if (ASIC_IS_AVIVO(rdev)) {
529 atombios_disable_ss(rdev, pll_id);
540 atombios_disable_ss(rdev, pll_id);
549 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
562 struct radeon_device *rdev = dev->dev_private;
576 if (ASIC_IS_AVIVO(rdev)) {
577 if ((rdev->family == CHIP_RS600) ||
578 (rdev->family == CHIP_RS690) ||
579 (rdev->family == CHIP_RS740))
583 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
588 if (rdev->family < CHIP_RV770)
591 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
594 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
597 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
625 if (ASIC_IS_AVIVO(rdev) &&
626 rdev->family != CHIP_RS780 &&
627 rdev->family != CHIP_RS880)
633 if (ASIC_IS_AVIVO(rdev)) {
670 if (ASIC_IS_DCE3(rdev)) {
676 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
694 atom_execute_table(rdev->mode_info.atom_context,
727 atom_execute_table(rdev->mode_info.atom_context,
766 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
776 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
796 if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
798 else if (ASIC_IS_DCE6(rdev))
812 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
830 struct radeon_device *rdev = dev->dev_private;
837 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
952 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
959 struct radeon_device *rdev = dev->dev_private;
987 if (ASIC_IS_DCE4(rdev))
989 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
995 radeon_atombios_get_ppll_ss_info(rdev,
1000 radeon_atombios_get_ppll_ss_info(rdev,
1005 radeon_atombios_get_ppll_ss_info(rdev,
1014 if (ASIC_IS_DCE4(rdev))
1016 radeon_atombios_get_asic_ss_info(rdev,
1022 radeon_atombios_get_ppll_ss_info(rdev,
1027 if (ASIC_IS_DCE4(rdev))
1029 radeon_atombios_get_asic_ss_info(rdev,
1035 if (ASIC_IS_DCE4(rdev))
1037 radeon_atombios_get_asic_ss_info(rdev,
1057 struct radeon_device *rdev = dev->dev_private;
1067 if (ASIC_IS_DCE5(rdev) &&
1074 pll = &rdev->clock.p1pll;
1077 pll = &rdev->clock.p2pll;
1082 pll = &rdev->clock.dcpll;
1095 else if (ASIC_IS_AVIVO(rdev))
1102 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1112 if (ASIC_IS_DCE4(rdev)) {
1129 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1140 struct radeon_device *rdev = dev->dev_private;
1269 if (rdev->family >= CHIP_TAHITI) {
1272 if (rdev->family >= CHIP_BONAIRE) {
1290 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1305 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
1311 if (rdev->family >= CHIP_CAYMAN)
1312 tmp = rdev->config.cayman.tile_config;
1314 tmp = rdev->config.evergreen.tile_config;
1335 if (rdev->family >= CHIP_BONAIRE) {
1342 if (rdev->family >= CHIP_BONAIRE) {
1346 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
1349 } else if ((rdev->family == CHIP_TAHITI) ||
1350 (rdev->family == CHIP_PITCAIRN))
1352 else if ((rdev->family == CHIP_VERDE) ||
1353 (rdev->family == CHIP_OLAND) ||
1354 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */
1419 if (rdev->family >= CHIP_BONAIRE)
1431 if ((rdev->family >= CHIP_BONAIRE) &&
1450 radeon_bandwidth_update(rdev);
1461 struct radeon_device *rdev = dev->dev_private;
1560 if (rdev->family >= CHIP_R600)
1576 if (rdev->family >= CHIP_R600) {
1599 if (rdev->family >= CHIP_RV770) {
1613 if (rdev->family >= CHIP_R600)
1658 radeon_bandwidth_update(rdev);
1667 struct radeon_device *rdev = dev->dev_private;
1669 if (ASIC_IS_DCE4(rdev))
1671 else if (ASIC_IS_AVIVO(rdev))
1682 struct radeon_device *rdev = dev->dev_private;
1684 if (ASIC_IS_DCE4(rdev))
1686 else if (ASIC_IS_AVIVO(rdev))
1696 struct radeon_device *rdev = dev->dev_private;
1753 struct radeon_device *rdev = dev->dev_private;
1764 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1787 struct radeon_device *rdev = dev->dev_private;
1804 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1866 struct radeon_device *rdev = dev->dev_private;
1872 if (ASIC_IS_DCE8(rdev)) {
1874 if (rdev->clock.dp_extclk)
1890 if ((rdev->family == CHIP_KABINI) ||
1891 (rdev->family == CHIP_MULLINS)) {
1912 } else if (ASIC_IS_DCE61(rdev)) {
1922 if (rdev->clock.dp_extclk)
1945 } else if (ASIC_IS_DCE41(rdev)) {
1948 if (rdev->clock.dp_extclk)
1959 } else if (ASIC_IS_DCE4(rdev)) {
1971 if (rdev->clock.dp_extclk)
1974 else if (ASIC_IS_DCE6(rdev))
1977 else if (ASIC_IS_DCE5(rdev))
2020 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
2023 if (ASIC_IS_DCE6(rdev))
2024 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2025 else if (ASIC_IS_DCE4(rdev)) {
2027 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
2029 rdev->clock.default_dispclk);
2031 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
2033 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2035 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
2047 struct radeon_device *rdev = dev->dev_private;
2061 if (ASIC_IS_DCE4(rdev))
2063 else if (ASIC_IS_AVIVO(rdev)) {
2128 struct radeon_device *rdev = dev->dev_private;
2131 if (ASIC_IS_DCE6(rdev))
2148 struct radeon_device *rdev = dev->dev_private;
2167 if (ASIC_IS_DCE4(rdev))
2169 else if (ASIC_IS_AVIVO(rdev))
2172 if (ASIC_IS_DCE6(rdev))
2175 for (i = 0; i < rdev->num_crtc; i++) {
2176 if (rdev->mode_info.crtcs[i] &&
2177 rdev->mode_info.crtcs[i]->enabled &&
2179 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
2196 if ((rdev->family == CHIP_ARUBA) ||
2197 (rdev->family == CHIP_KAVERI) ||
2198 (rdev->family == CHIP_BONAIRE) ||
2199 (rdev->family == CHIP_HAWAII))
2228 struct radeon_device *rdev = dev->dev_private;
2230 if (ASIC_IS_DCE4(rdev)) {