Lines Matching defs:clock

566 	u32 adjusted_clock = mode->clock;
568 u32 dp_clock = mode->clock;
569 u32 clock = mode->clock;
571 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
583 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
597 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
602 if (mode->clock > 200000) /* range limits??? */
634 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
636 adjusted_clock = mode->clock * 2;
655 clock = (clock * 5) / 4;
658 clock = (clock * 3) / 2;
661 clock = clock * 2;
666 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
687 args.v1.usPixelClock = cpu_to_le16(clock / 10);
699 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
784 /* if the default dcpll clock is specified,
792 /* if the default dcpll clock is specified,
820 u32 clock,
845 if (clock == ATOM_DISABLE)
847 args.v1.usPixelClock = cpu_to_le16(clock / 10);
857 args.v2.usPixelClock = cpu_to_le16(clock / 10);
867 args.v3.usPixelClock = cpu_to_le16(clock / 10);
884 args.v5.usPixelClock = cpu_to_le16(clock / 10);
913 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
978 /* Assign mode clock for hdmi deep color max clock limit check */
979 radeon_connector->pixelclock_for_modeset = mode->clock;
1019 mode->clock / 10);
1032 mode->clock / 10);
1040 mode->clock / 10);
1047 /* adjust pixel clock as needed */
1060 u32 pll_clock = mode->clock;
1061 u32 clock = mode->clock;
1066 /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */
1070 clock = radeon_crtc->adjusted_clock;
1074 pll = &rdev->clock.p1pll;
1077 pll = &rdev->clock.p2pll;
1082 pll = &rdev->clock.dcpll;
1106 encoder_mode, radeon_encoder->encoder_id, clock,
1781 * be shared (i.e., same clock).
1813 /* for non-DP check the clock */
1815 if ((crtc->mode.clock == test_crtc->mode.clock) &&
1874 if (rdev->clock.dp_extclk)
1875 /* skip PPLL programming if using ext clock */
1884 /* use the same PPLL for all monitors with the same clock */
1922 if (rdev->clock.dp_extclk)
1923 /* skip PPLL programming if using ext clock */
1932 /* use the same PPLL for all monitors with the same clock */
1948 if (rdev->clock.dp_extclk)
1949 /* skip PPLL programming if using ext clock */
1960 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1962 * DCE4: PPLL or ext clock
1963 * DCE5: PPLL, DCPLL, or ext clock
1964 * DCE6: PPLL, PPLL0, or ext clock
1968 * crtc virtual pixel clock.
1971 if (rdev->clock.dp_extclk)
1972 /* skip PPLL programming if using ext clock */
1987 /* use the same PPLL for all monitors with the same clock */
2011 * both use same clock.
2024 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2029 rdev->clock.default_dispclk);
2033 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);