Lines Matching defs:pfdev
24 struct panfrost_device *pfdev = data;
25 u32 state = gpu_read(pfdev, GPU_INT_STAT);
26 u32 fault_status = gpu_read(pfdev, GPU_FAULT_STATUS);
32 u64 address = (u64) gpu_read(pfdev, GPU_FAULT_ADDRESS_HI) << 32;
33 address |= gpu_read(pfdev, GPU_FAULT_ADDRESS_LO);
35 dev_warn(pfdev->dev, "GPU Fault 0x%08x (%s) at 0x%016llx\n",
40 dev_warn(pfdev->dev, "There were multiple GPU faults - some have not been reported\n");
42 gpu_write(pfdev, GPU_INT_MASK, 0);
46 panfrost_perfcnt_sample_done(pfdev);
49 panfrost_perfcnt_clean_cache_done(pfdev);
51 gpu_write(pfdev, GPU_INT_CLEAR, state);
56 int panfrost_gpu_soft_reset(struct panfrost_device *pfdev)
61 gpu_write(pfdev, GPU_INT_MASK, 0);
62 gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED);
63 gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET);
65 ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT,
69 dev_err(pfdev->dev, "gpu soft reset timed out\n");
73 gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_MASK_ALL);
76 gpu_write(pfdev, GPU_INT_MASK,
84 void panfrost_gpu_amlogic_quirk(struct panfrost_device *pfdev)
91 gpu_write(pfdev, GPU_PWR_KEY, GPU_PWR_KEY_UNLOCK);
92 gpu_write(pfdev, GPU_PWR_OVERRIDE1, 0xfff | (0x20 << 16));
95 static void panfrost_gpu_init_quirks(struct panfrost_device *pfdev)
99 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_8443) ||
100 panfrost_has_hw_issue(pfdev, HW_ISSUE_11035))
103 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10327))
106 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10797))
109 if (!panfrost_has_hw_issue(pfdev, GPUCORE_1619)) {
110 if (panfrost_model_cmp(pfdev, 0x750) < 0) /* T60x, T62x, T72x */
112 else if (panfrost_model_cmp(pfdev, 0x880) <= 0) /* T76x, T8xx */
116 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_TTRX_2968_TTRX_3162))
119 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_TLS_HASHING))
123 gpu_write(pfdev, GPU_SHADER_CONFIG, quirks);
126 quirks = gpu_read(pfdev, GPU_TILER_CONFIG);
129 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_T76X_3953))
132 gpu_write(pfdev, GPU_TILER_CONFIG, quirks);
136 if ((panfrost_model_eq(pfdev, 0x860) || panfrost_model_eq(pfdev, 0x880)) &&
137 pfdev->features.revision >= 0x2000)
139 else if (panfrost_model_eq(pfdev, 0x6000) &&
140 pfdev->features.coherency_features == COHERENCY_ACE)
144 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_IDVS_GROUP_SIZE))
148 gpu_write(pfdev, GPU_JM_CONFIG, quirks);
151 if (pfdev->comp->vendor_quirk)
152 pfdev->comp->vendor_quirk(pfdev);
222 static void panfrost_gpu_init_features(struct panfrost_device *pfdev)
231 pfdev->features.l2_features = gpu_read(pfdev, GPU_L2_FEATURES);
232 pfdev->features.core_features = gpu_read(pfdev, GPU_CORE_FEATURES);
233 pfdev->features.tiler_features = gpu_read(pfdev, GPU_TILER_FEATURES);
234 pfdev->features.mem_features = gpu_read(pfdev, GPU_MEM_FEATURES);
235 pfdev->features.mmu_features = gpu_read(pfdev, GPU_MMU_FEATURES);
236 pfdev->features.thread_features = gpu_read(pfdev, GPU_THREAD_FEATURES);
237 pfdev->features.max_threads = gpu_read(pfdev, GPU_THREAD_MAX_THREADS);
238 pfdev->features.thread_max_workgroup_sz = gpu_read(pfdev, GPU_THREAD_MAX_WORKGROUP_SIZE);
239 pfdev->features.thread_max_barrier_sz = gpu_read(pfdev, GPU_THREAD_MAX_BARRIER_SIZE);
240 pfdev->features.coherency_features = gpu_read(pfdev, GPU_COHERENCY_FEATURES);
241 pfdev->features.afbc_features = gpu_read(pfdev, GPU_AFBC_FEATURES);
243 pfdev->features.texture_features[i] = gpu_read(pfdev, GPU_TEXTURE_FEATURES(i));
245 pfdev->features.as_present = gpu_read(pfdev, GPU_AS_PRESENT);
247 pfdev->features.js_present = gpu_read(pfdev, GPU_JS_PRESENT);
248 num_js = hweight32(pfdev->features.js_present);
250 pfdev->features.js_features[i] = gpu_read(pfdev, GPU_JS_FEATURES(i));
252 pfdev->features.shader_present = gpu_read(pfdev, GPU_SHADER_PRESENT_LO);
253 pfdev->features.shader_present |= (u64)gpu_read(pfdev, GPU_SHADER_PRESENT_HI) << 32;
255 pfdev->features.tiler_present = gpu_read(pfdev, GPU_TILER_PRESENT_LO);
256 pfdev->features.tiler_present |= (u64)gpu_read(pfdev, GPU_TILER_PRESENT_HI) << 32;
258 pfdev->features.l2_present = gpu_read(pfdev, GPU_L2_PRESENT_LO);
259 pfdev->features.l2_present |= (u64)gpu_read(pfdev, GPU_L2_PRESENT_HI) << 32;
260 pfdev->features.nr_core_groups = hweight64(pfdev->features.l2_present);
262 pfdev->features.stack_present = gpu_read(pfdev, GPU_STACK_PRESENT_LO);
263 pfdev->features.stack_present |= (u64)gpu_read(pfdev, GPU_STACK_PRESENT_HI) << 32;
265 pfdev->features.thread_tls_alloc = gpu_read(pfdev, GPU_THREAD_TLS_ALLOC);
267 gpu_id = gpu_read(pfdev, GPU_ID);
268 pfdev->features.revision = gpu_id & 0xffff;
269 pfdev->features.id = gpu_id >> 16;
274 if (pfdev->features.id == 0x6956)
275 pfdev->features.id = 0x0600;
277 major = (pfdev->features.revision >> 12) & 0xf;
278 minor = (pfdev->features.revision >> 4) & 0xff;
279 status = pfdev->features.revision & 0xf;
280 rev = pfdev->features.revision;
282 gpu_id = pfdev->features.id;
287 if (!panfrost_model_eq(pfdev, model->id))
307 bitmap_from_u64(pfdev->features.hw_features, hw_feat);
308 bitmap_from_u64(pfdev->features.hw_issues, hw_issues);
310 dev_info(pfdev->dev, "mali-%s id 0x%x major 0x%x minor 0x%x status 0x%x",
312 dev_info(pfdev->dev, "features: %64pb, issues: %64pb",
313 pfdev->features.hw_features,
314 pfdev->features.hw_issues);
316 dev_info(pfdev->dev, "Features: L2:0x%08x Shader:0x%08x Tiler:0x%08x Mem:0x%0x MMU:0x%08x AS:0x%x JS:0x%x",
317 pfdev->features.l2_features,
318 pfdev->features.core_features,
319 pfdev->features.tiler_features,
320 pfdev->features.mem_features,
321 pfdev->features.mmu_features,
322 pfdev->features.as_present,
323 pfdev->features.js_present);
325 dev_info(pfdev->dev, "shader_present=0x%0llx l2_present=0x%0llx",
326 pfdev->features.shader_present, pfdev->features.l2_present);
329 static u64 panfrost_get_core_mask(struct panfrost_device *pfdev)
333 if (pfdev->features.l2_present == 1)
343 core_mask = ~(pfdev->features.l2_present - 1) &
344 (pfdev->features.l2_present - 2);
345 dev_info_once(pfdev->dev, "using only 1st core group (%lu cores from %lu)\n",
347 hweight64(pfdev->features.shader_present));
352 void panfrost_gpu_power_on(struct panfrost_device *pfdev)
358 panfrost_gpu_init_quirks(pfdev);
359 core_mask = panfrost_get_core_mask(pfdev);
361 gpu_write(pfdev, L2_PWRON_LO, pfdev->features.l2_present & core_mask);
362 ret = readl_relaxed_poll_timeout(pfdev->iomem + L2_READY_LO,
363 val, val == (pfdev->features.l2_present & core_mask),
366 dev_err(pfdev->dev, "error powering up gpu L2");
368 gpu_write(pfdev, SHADER_PWRON_LO,
369 pfdev->features.shader_present & core_mask);
370 ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_READY_LO,
371 val, val == (pfdev->features.shader_present & core_mask),
374 dev_err(pfdev->dev, "error powering up gpu shader");
376 gpu_write(pfdev, TILER_PWRON_LO, pfdev->features.tiler_present);
377 ret = readl_relaxed_poll_timeout(pfdev->iomem + TILER_READY_LO,
378 val, val == pfdev->features.tiler_present, 100, 1000);
380 dev_err(pfdev->dev, "error powering up gpu tiler");
383 void panfrost_gpu_power_off(struct panfrost_device *pfdev)
388 gpu_write(pfdev, SHADER_PWROFF_LO, pfdev->features.shader_present);
389 ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_PWRTRANS_LO,
392 dev_err(pfdev->dev, "shader power transition timeout");
394 gpu_write(pfdev, TILER_PWROFF_LO, pfdev->features.tiler_present);
395 ret = readl_relaxed_poll_timeout(pfdev->iomem + TILER_PWRTRANS_LO,
398 dev_err(pfdev->dev, "tiler power transition timeout");
400 gpu_write(pfdev, L2_PWROFF_LO, pfdev->features.l2_present);
401 ret = readl_poll_timeout(pfdev->iomem + L2_PWRTRANS_LO,
404 dev_err(pfdev->dev, "l2 power transition timeout");
407 int panfrost_gpu_init(struct panfrost_device *pfdev)
411 err = panfrost_gpu_soft_reset(pfdev);
415 panfrost_gpu_init_features(pfdev);
417 err = dma_set_mask_and_coherent(pfdev->dev,
418 DMA_BIT_MASK(FIELD_GET(0xff00, pfdev->features.mmu_features)));
422 dma_set_max_seg_size(pfdev->dev, UINT_MAX);
424 irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "gpu");
428 err = devm_request_irq(pfdev->dev, irq, panfrost_gpu_irq_handler,
429 IRQF_SHARED, KBUILD_MODNAME "-gpu", pfdev);
431 dev_err(pfdev->dev, "failed to request gpu irq");
435 panfrost_gpu_power_on(pfdev);
440 void panfrost_gpu_fini(struct panfrost_device *pfdev)
442 panfrost_gpu_power_off(pfdev);
445 u32 panfrost_gpu_get_latest_flush_id(struct panfrost_device *pfdev)
449 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_FLUSH_REDUCTION)) {
451 if (pm_runtime_get_if_in_use(pfdev->dev)) {
452 flush_id = gpu_read(pfdev, GPU_LATEST_FLUSH_ID);
453 pm_runtime_put(pfdev->dev);