Lines Matching refs:dsi
48 #include "dsi.h"
50 #define REG_GET(dsi, idx, start, end) \
51 FLD_GET(dsi_read_reg(dsi, idx), start, end)
53 #define REG_FLD_MOD(dsi, idx, val, start, end) \
54 dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end))
56 static int dsi_init_dispc(struct dsi_data *dsi);
57 static void dsi_uninit_dispc(struct dsi_data *dsi);
59 static int dsi_vc_send_null(struct dsi_data *dsi, int vc, int channel);
61 static ssize_t _omap_dsi_host_transfer(struct dsi_data *dsi, int vc,
86 static inline void dsi_write_reg(struct dsi_data *dsi,
92 case DSI_PROTO: base = dsi->proto_base; break;
93 case DSI_PHY: base = dsi->phy_base; break;
94 case DSI_PLL: base = dsi->pll_base; break;
101 static inline u32 dsi_read_reg(struct dsi_data *dsi, const struct dsi_reg idx)
106 case DSI_PROTO: base = dsi->proto_base; break;
107 case DSI_PHY: base = dsi->phy_base; break;
108 case DSI_PLL: base = dsi->pll_base; break;
115 static void dsi_bus_lock(struct dsi_data *dsi)
117 down(&dsi->bus_lock);
120 static void dsi_bus_unlock(struct dsi_data *dsi)
122 up(&dsi->bus_lock);
125 static bool dsi_bus_is_locked(struct dsi_data *dsi)
127 return dsi->bus_lock.count == 0;
135 static inline bool wait_for_bit_change(struct dsi_data *dsi,
146 if (REG_GET(dsi, idx, bitnum, bitnum) == value)
153 if (REG_GET(dsi, idx, bitnum, bitnum) == value)
165 static void dsi_perf_mark_setup(struct dsi_data *dsi)
167 dsi->perf_setup_time = ktime_get();
170 static void dsi_perf_mark_start(struct dsi_data *dsi)
172 dsi->perf_start_time = ktime_get();
175 static void dsi_perf_show(struct dsi_data *dsi, const char *name)
186 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
191 trans_time = ktime_sub(t, dsi->perf_start_time);
198 total_bytes = dsi->update_bytes;
210 static inline void dsi_perf_mark_setup(struct dsi_data *dsi)
214 static inline void dsi_perf_mark_start(struct dsi_data *dsi)
218 static inline void dsi_perf_show(struct dsi_data *dsi, const char *name)
315 static void dsi_collect_irq_stats(struct dsi_data *dsi, u32 irqstatus,
320 spin_lock(&dsi->irq_stats_lock);
322 dsi->irq_stats.irq_count++;
323 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
326 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
328 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
330 spin_unlock(&dsi->irq_stats_lock);
333 #define dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus)
338 static void dsi_handle_irq_errors(struct dsi_data *dsi, u32 irqstatus,
346 spin_lock(&dsi->errors_lock);
347 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
348 spin_unlock(&dsi->errors_lock);
409 struct dsi_data *dsi = arg;
413 if (!dsi->is_enabled)
416 spin_lock(&dsi->irq_lock);
418 irqstatus = dsi_read_reg(dsi, DSI_IRQSTATUS);
422 spin_unlock(&dsi->irq_lock);
426 dsi_write_reg(dsi, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
428 dsi_read_reg(dsi, DSI_IRQSTATUS);
436 vcstatus[i] = dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i));
438 dsi_write_reg(dsi, DSI_VC_IRQSTATUS(i), vcstatus[i]);
440 dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i));
444 ciostatus = dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS);
446 dsi_write_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
448 dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS);
455 del_timer(&dsi->te_timer);
460 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
461 sizeof(dsi->isr_tables));
463 spin_unlock(&dsi->irq_lock);
465 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
467 dsi_handle_irq_errors(dsi, irqstatus, vcstatus, ciostatus);
469 dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus);
474 /* dsi->irq_lock has to be locked by the caller */
475 static void _omap_dsi_configure_irqs(struct dsi_data *dsi,
498 old_mask = dsi_read_reg(dsi, enable_reg);
500 dsi_write_reg(dsi, status_reg, (mask ^ old_mask) & mask);
501 dsi_write_reg(dsi, enable_reg, mask);
504 dsi_read_reg(dsi, enable_reg);
505 dsi_read_reg(dsi, status_reg);
508 /* dsi->irq_lock has to be locked by the caller */
509 static void _omap_dsi_set_irqs(struct dsi_data *dsi)
515 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table,
516 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
520 /* dsi->irq_lock has to be locked by the caller */
521 static void _omap_dsi_set_irqs_vc(struct dsi_data *dsi, int vc)
523 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_vc[vc],
524 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
529 /* dsi->irq_lock has to be locked by the caller */
530 static void _omap_dsi_set_irqs_cio(struct dsi_data *dsi)
532 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_cio,
533 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
538 static void _dsi_initialize_irq(struct dsi_data *dsi)
543 spin_lock_irqsave(&dsi->irq_lock, flags);
545 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
547 _omap_dsi_set_irqs(dsi);
549 _omap_dsi_set_irqs_vc(dsi, vc);
550 _omap_dsi_set_irqs_cio(dsi);
552 spin_unlock_irqrestore(&dsi->irq_lock, flags);
611 static int dsi_register_isr(struct dsi_data *dsi, omap_dsi_isr_t isr,
617 spin_lock_irqsave(&dsi->irq_lock, flags);
619 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
620 ARRAY_SIZE(dsi->isr_tables.isr_table));
623 _omap_dsi_set_irqs(dsi);
625 spin_unlock_irqrestore(&dsi->irq_lock, flags);
630 static int dsi_unregister_isr(struct dsi_data *dsi, omap_dsi_isr_t isr,
636 spin_lock_irqsave(&dsi->irq_lock, flags);
638 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
639 ARRAY_SIZE(dsi->isr_tables.isr_table));
642 _omap_dsi_set_irqs(dsi);
644 spin_unlock_irqrestore(&dsi->irq_lock, flags);
649 static int dsi_register_isr_vc(struct dsi_data *dsi, int vc,
655 spin_lock_irqsave(&dsi->irq_lock, flags);
658 dsi->isr_tables.isr_table_vc[vc],
659 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]));
662 _omap_dsi_set_irqs_vc(dsi, vc);
664 spin_unlock_irqrestore(&dsi->irq_lock, flags);
669 static int dsi_unregister_isr_vc(struct dsi_data *dsi, int vc,
675 spin_lock_irqsave(&dsi->irq_lock, flags);
678 dsi->isr_tables.isr_table_vc[vc],
679 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]));
682 _omap_dsi_set_irqs_vc(dsi, vc);
684 spin_unlock_irqrestore(&dsi->irq_lock, flags);
689 static u32 dsi_get_errors(struct dsi_data *dsi)
694 spin_lock_irqsave(&dsi->errors_lock, flags);
695 e = dsi->errors;
696 dsi->errors = 0;
697 spin_unlock_irqrestore(&dsi->errors_lock, flags);
701 static int dsi_runtime_get(struct dsi_data *dsi)
707 r = pm_runtime_get_sync(dsi->dev);
709 pm_runtime_put_noidle(dsi->dev);
715 static void dsi_runtime_put(struct dsi_data *dsi)
721 r = pm_runtime_put_sync(dsi->dev);
725 static void _dsi_print_reset_status(struct dsi_data *dsi)
732 dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
734 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) {
745 FLD_GET(dsi_read_reg(dsi, DSI_##fld), start, end)
760 static inline int dsi_if_enable(struct dsi_data *dsi, bool enable)
765 REG_FLD_MOD(dsi, DSI_CTRL, enable, 0, 0); /* IF_EN */
767 if (!wait_for_bit_change(dsi, DSI_CTRL, 0, enable)) {
775 static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct dsi_data *dsi)
777 return dsi->pll.cinfo.clkout[HSDIV_DISPC];
780 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct dsi_data *dsi)
782 return dsi->pll.cinfo.clkout[HSDIV_DSI];
785 static unsigned long dsi_get_txbyteclkhs(struct dsi_data *dsi)
787 return dsi->pll.cinfo.clkdco / 16;
790 static unsigned long dsi_fclk_rate(struct dsi_data *dsi)
795 source = dss_get_dsi_clk_source(dsi->dss, dsi->module_id);
798 r = clk_get_rate(dsi->dss_clk);
801 r = dsi_get_pll_hsdiv_dsi_rate(dsi);
826 static int dsi_set_lp_clk_divisor(struct dsi_data *dsi)
831 unsigned int lpdiv_max = dsi->data->max_pll_lpdiv;
834 lp_clk_div = dsi->user_lp_cinfo.lp_clk_div;
839 dsi_fclk = dsi_fclk_rate(dsi);
844 dsi->current_lp_cinfo.lp_clk = lp_clk;
845 dsi->current_lp_cinfo.lp_clk_div = lp_clk_div;
848 REG_FLD_MOD(dsi, DSI_CLK_CTRL, lp_clk_div, 12, 0);
851 REG_FLD_MOD(dsi, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
856 static void dsi_enable_scp_clk(struct dsi_data *dsi)
858 if (dsi->scp_clk_refcount++ == 0)
859 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
862 static void dsi_disable_scp_clk(struct dsi_data *dsi)
864 WARN_ON(dsi->scp_clk_refcount == 0);
865 if (--dsi->scp_clk_refcount == 0)
866 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
876 static int dsi_pll_power(struct dsi_data *dsi, enum dsi_pll_power_state state)
881 if ((dsi->data->quirks & DSI_QUIRK_PLL_PWR_BUG) &&
886 REG_FLD_MOD(dsi, DSI_CLK_CTRL, state, 31, 30);
889 while (FLD_GET(dsi_read_reg(dsi, DSI_CLK_CTRL), 29, 28) != state) {
902 static void dsi_pll_calc_dsi_fck(struct dsi_data *dsi,
907 max_dsi_fck = dsi->data->max_fck_freq;
915 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
920 r = dsi_runtime_get(dsi);
927 dsi_enable_scp_clk(dsi);
929 r = regulator_enable(dsi->vdds_dsi_reg);
934 dispc_pck_free_enable(dsi->dss->dispc, 1);
936 if (!wait_for_bit_change(dsi, DSI_PLL_STATUS, 0, 1)) {
939 dispc_pck_free_enable(dsi->dss->dispc, 0);
945 dispc_pck_free_enable(dsi->dss->dispc, 0);
947 r = dsi_pll_power(dsi, DSI_PLL_POWER_ON_ALL);
956 regulator_disable(dsi->vdds_dsi_reg);
958 dsi_disable_scp_clk(dsi);
959 dsi_runtime_put(dsi);
965 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
967 dsi_pll_power(dsi, DSI_PLL_POWER_OFF);
969 regulator_disable(dsi->vdds_dsi_reg);
971 dsi_disable_scp_clk(dsi);
972 dsi_runtime_put(dsi);
979 struct dsi_data *dsi = s->private;
980 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo;
982 int dsi_module = dsi->module_id;
983 struct dss_pll *pll = &dsi->pll;
985 dispc_clk_src = dss_get_dispc_clk_source(dsi->dss);
986 dsi_clk_src = dss_get_dsi_clk_source(dsi->dss, dsi_module);
988 if (dsi_runtime_get(dsi))
993 seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin));
1020 seq_printf(s, "dsi fclk source = %s\n",
1023 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsi));
1028 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsi));
1030 seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk);
1032 dsi_runtime_put(dsi);
1040 struct dsi_data *dsi = s->private;
1048 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1050 *stats = dsi->irq_stats;
1051 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1052 dsi->irq_stats.last_reset = jiffies;
1054 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1063 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1137 struct dsi_data *dsi = s->private;
1139 if (dsi_runtime_get(dsi))
1141 dsi_enable_scp_clk(dsi);
1143 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsi, r))
1215 dsi_disable_scp_clk(dsi);
1216 dsi_runtime_put(dsi);
1227 static int dsi_cio_power(struct dsi_data *dsi, enum dsi_cio_power_state state)
1232 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG1, state, 28, 27);
1235 while (FLD_GET(dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1),
1248 static unsigned int dsi_get_line_buf_size(struct dsi_data *dsi)
1256 if (!(dsi->data->quirks & DSI_QUIRK_GNQ))
1259 val = REG_GET(dsi, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
1282 static int dsi_set_lane_config(struct dsi_data *dsi)
1295 r = dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1);
1297 for (i = 0; i < dsi->num_lanes_used; ++i) {
1302 for (t = 0; t < dsi->num_lanes_supported; ++t)
1303 if (dsi->lanes[t].function == functions[i])
1306 if (t == dsi->num_lanes_supported)
1310 polarity = dsi->lanes[t].polarity;
1317 for (; i < dsi->num_lanes_supported; ++i) {
1324 dsi_write_reg(dsi, DSI_COMPLEXIO_CFG1, r);
1329 static inline unsigned int ns2ddr(struct dsi_data *dsi, unsigned int ns)
1332 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1337 static inline unsigned int ddr2ns(struct dsi_data *dsi, unsigned int ddr)
1339 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1344 static void dsi_cio_timings(struct dsi_data *dsi)
1356 ths_prepare = ns2ddr(dsi, 70) + 2;
1359 ths_prepare_ths_zero = ns2ddr(dsi, 175) + 2;
1362 ths_trail = ns2ddr(dsi, 60) + 5;
1365 ths_exit = ns2ddr(dsi, 145);
1368 tlpx_half = ns2ddr(dsi, 25);
1371 tclk_trail = ns2ddr(dsi, 60) + 2;
1374 tclk_prepare = ns2ddr(dsi, 65);
1377 tclk_zero = ns2ddr(dsi, 260);
1380 ths_prepare, ddr2ns(dsi, ths_prepare),
1381 ths_prepare_ths_zero, ddr2ns(dsi, ths_prepare_ths_zero));
1383 ths_trail, ddr2ns(dsi, ths_trail),
1384 ths_exit, ddr2ns(dsi, ths_exit));
1388 tlpx_half, ddr2ns(dsi, tlpx_half),
1389 tclk_trail, ddr2ns(dsi, tclk_trail),
1390 tclk_zero, ddr2ns(dsi, tclk_zero));
1392 tclk_prepare, ddr2ns(dsi, tclk_prepare));
1396 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
1401 dsi_write_reg(dsi, DSI_DSIPHY_CFG0, r);
1403 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
1408 if (dsi->data->quirks & DSI_QUIRK_PHY_DCC) {
1414 dsi_write_reg(dsi, DSI_DSIPHY_CFG1, r);
1416 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2);
1418 dsi_write_reg(dsi, DSI_DSIPHY_CFG2, r);
1421 static int dsi_cio_wait_tx_clk_esc_reset(struct dsi_data *dsi)
1429 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC)
1434 for (i = 0; i < dsi->num_lanes_supported; ++i)
1435 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
1442 l = dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
1445 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1450 if (ok == dsi->num_lanes_supported)
1454 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1469 static unsigned int dsi_get_lane_mask(struct dsi_data *dsi)
1474 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1475 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
1494 static int dsi_omap4_mux_pads(struct dsi_data *dsi, unsigned int lanes)
1499 if (dsi->module_id == 0) {
1504 } else if (dsi->module_id == 1) {
1513 return regmap_update_bits(dsi->syscon, OMAP4_DSIPHY_SYSCON_OFFSET,
1526 static int dsi_omap5_mux_pads(struct dsi_data *dsi, unsigned int lanes)
1530 if (dsi->module_id == 0)
1532 else if (dsi->module_id == 1)
1537 return regmap_update_bits(dsi->syscon, OMAP5_DSIPHY_SYSCON_OFFSET,
1542 static int dsi_enable_pads(struct dsi_data *dsi, unsigned int lane_mask)
1544 if (dsi->data->model == DSI_MODEL_OMAP4)
1545 return dsi_omap4_mux_pads(dsi, lane_mask);
1546 if (dsi->data->model == DSI_MODEL_OMAP5)
1547 return dsi_omap5_mux_pads(dsi, lane_mask);
1551 static void dsi_disable_pads(struct dsi_data *dsi)
1553 if (dsi->data->model == DSI_MODEL_OMAP4)
1554 dsi_omap4_mux_pads(dsi, 0);
1555 else if (dsi->data->model == DSI_MODEL_OMAP5)
1556 dsi_omap5_mux_pads(dsi, 0);
1559 static int dsi_cio_init(struct dsi_data *dsi)
1566 r = dsi_enable_pads(dsi, dsi_get_lane_mask(dsi));
1570 dsi_enable_scp_clk(dsi);
1575 dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
1577 if (!wait_for_bit_change(dsi, DSI_DSIPHY_CFG5, 30, 1)) {
1583 r = dsi_set_lane_config(dsi);
1588 l = dsi_read_reg(dsi, DSI_TIMING1);
1593 dsi_write_reg(dsi, DSI_TIMING1, l);
1595 r = dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_ON);
1599 if (!wait_for_bit_change(dsi, DSI_COMPLEXIO_CFG1, 29, 1)) {
1605 dsi_if_enable(dsi, true);
1606 dsi_if_enable(dsi, false);
1607 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
1609 r = dsi_cio_wait_tx_clk_esc_reset(dsi);
1614 REG_FLD_MOD(dsi, DSI_TIMING1, 0, 15, 15);
1616 dsi_cio_timings(dsi);
1619 REG_FLD_MOD(dsi, DSI_CLK_CTRL,
1620 !(dsi->dsidev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS),
1628 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
1630 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF);
1633 dsi_disable_scp_clk(dsi);
1634 dsi_disable_pads(dsi);
1638 static void dsi_cio_uninit(struct dsi_data *dsi)
1641 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13);
1643 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF);
1644 dsi_disable_scp_clk(dsi);
1645 dsi_disable_pads(dsi);
1648 static void dsi_config_tx_fifo(struct dsi_data *dsi,
1656 dsi->vc[0].tx_fifo_size = size1;
1657 dsi->vc[1].tx_fifo_size = size2;
1658 dsi->vc[2].tx_fifo_size = size3;
1659 dsi->vc[3].tx_fifo_size = size4;
1663 int size = dsi->vc[i].tx_fifo_size;
1677 dsi_write_reg(dsi, DSI_TX_FIFO_VC_SIZE, r);
1680 static void dsi_config_rx_fifo(struct dsi_data *dsi,
1688 dsi->vc[0].rx_fifo_size = size1;
1689 dsi->vc[1].rx_fifo_size = size2;
1690 dsi->vc[2].rx_fifo_size = size3;
1691 dsi->vc[3].rx_fifo_size = size4;
1695 int size = dsi->vc[i].rx_fifo_size;
1709 dsi_write_reg(dsi, DSI_RX_FIFO_VC_SIZE, r);
1712 static int dsi_force_tx_stop_mode_io(struct dsi_data *dsi)
1716 r = dsi_read_reg(dsi, DSI_TIMING1);
1718 dsi_write_reg(dsi, DSI_TIMING1, r);
1720 if (!wait_for_bit_change(dsi, DSI_TIMING1, 15, 0)) {
1728 static bool dsi_vc_is_enabled(struct dsi_data *dsi, int vc)
1730 return REG_GET(dsi, DSI_VC_CTRL(vc), 0, 0);
1737 struct dsi_data *dsi = vp_data->dsi;
1738 const int vc = dsi->update_vc;
1739 u8 bit = dsi->te_enabled ? 30 : 31;
1741 if (REG_GET(dsi, DSI_VC_TE(vc), bit, bit) == 0)
1745 static int dsi_sync_vc_vp(struct dsi_data *dsi, int vc)
1749 .dsi = dsi,
1755 bit = dsi->te_enabled ? 30 : 31;
1757 r = dsi_register_isr_vc(dsi, vc, dsi_packet_sent_handler_vp,
1763 if (REG_GET(dsi, DSI_VC_TE(vc), bit, bit)) {
1772 dsi_unregister_isr_vc(dsi, vc, dsi_packet_sent_handler_vp,
1777 dsi_unregister_isr_vc(dsi, vc, dsi_packet_sent_handler_vp,
1787 struct dsi_data *dsi = l4_data->dsi;
1788 const int vc = dsi->update_vc;
1790 if (REG_GET(dsi, DSI_VC_CTRL(vc), 5, 5) == 0)
1794 static int dsi_sync_vc_l4(struct dsi_data *dsi, int vc)
1798 .dsi = dsi,
1803 r = dsi_register_isr_vc(dsi, vc, dsi_packet_sent_handler_l4,
1809 if (REG_GET(dsi, DSI_VC_CTRL(vc), 5, 5)) {
1818 dsi_unregister_isr_vc(dsi, vc, dsi_packet_sent_handler_l4,
1823 dsi_unregister_isr_vc(dsi, vc, dsi_packet_sent_handler_l4,
1829 static int dsi_sync_vc(struct dsi_data *dsi, int vc)
1831 WARN_ON(!dsi_bus_is_locked(dsi));
1835 if (!dsi_vc_is_enabled(dsi, vc))
1838 switch (dsi->vc[vc].source) {
1840 return dsi_sync_vc_vp(dsi, vc);
1842 return dsi_sync_vc_l4(dsi, vc);
1849 static int dsi_vc_enable(struct dsi_data *dsi, int vc, bool enable)
1856 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), enable, 0, 0);
1858 if (!wait_for_bit_change(dsi, DSI_VC_CTRL(vc), 0, enable)) {
1866 static void dsi_vc_initial_config(struct dsi_data *dsi, int vc)
1872 r = dsi_read_reg(dsi, DSI_VC_CTRL(vc));
1885 if (dsi->data->quirks & DSI_QUIRK_VC_OCP_WIDTH)
1891 dsi_write_reg(dsi, DSI_VC_CTRL(vc), r);
1893 dsi->vc[vc].source = DSI_VC_SOURCE_L4;
1899 struct dsi_data *dsi = to_dsi_data(dssdev);
1903 if (REG_GET(dsi, DSI_VC_CTRL(vc), 9, 9) == enable)
1906 WARN_ON(!dsi_bus_is_locked(dsi));
1908 dsi_vc_enable(dsi, vc, 0);
1909 dsi_if_enable(dsi, 0);
1911 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), enable, 9, 9);
1913 dsi_vc_enable(dsi, vc, 1);
1914 dsi_if_enable(dsi, 1);
1916 dsi_force_tx_stop_mode_io(dsi);
1919 static void dsi_vc_flush_long_data(struct dsi_data *dsi, int vc)
1921 while (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) {
1923 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc));
1969 static u16 dsi_vc_flush_receive_data(struct dsi_data *dsi, int vc)
1972 while (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) {
1975 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc));
1990 dsi_vc_flush_long_data(dsi, vc);
1998 static int dsi_vc_send_bta(struct dsi_data *dsi, int vc)
2000 if (dsi->debug_write || dsi->debug_read)
2003 WARN_ON(!dsi_bus_is_locked(dsi));
2006 if (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) {
2008 dsi_vc_flush_receive_data(dsi, vc);
2011 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), 1, 6, 6); /* BTA_EN */
2014 dsi_read_reg(dsi, DSI_VC_CTRL(vc));
2021 struct dsi_data *dsi = to_dsi_data(dssdev);
2026 r = dsi_register_isr_vc(dsi, vc, dsi_completion_handler,
2031 r = dsi_register_isr(dsi, dsi_completion_handler, &completion,
2036 r = dsi_vc_send_bta(dsi, vc);
2047 err = dsi_get_errors(dsi);
2054 dsi_unregister_isr(dsi, dsi_completion_handler, &completion,
2057 dsi_unregister_isr_vc(dsi, vc, dsi_completion_handler,
2063 static inline void dsi_vc_write_long_header(struct dsi_data *dsi, int vc,
2070 WARN_ON(!dsi_bus_is_locked(dsi));
2077 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_HEADER(vc), val);
2080 static inline void dsi_vc_write_long_payload(struct dsi_data *dsi, int vc,
2090 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_PAYLOAD(vc), val);
2093 static int dsi_vc_send_long(struct dsi_data *dsi, int vc,
2102 if (dsi->debug_write)
2106 if (dsi->vc[vc].tx_fifo_size * 32 * 4 < msg->tx_len + 4) {
2111 dsi_vc_write_long_header(dsi, vc, msg->channel, msg->type, msg->tx_len, 0);
2115 if (dsi->debug_write)
2123 dsi_vc_write_long_payload(dsi, vc, b1, b2, b3, b4);
2130 if (dsi->debug_write)
2148 dsi_vc_write_long_payload(dsi, vc, b1, b2, b3, 0);
2154 static int dsi_vc_send_short(struct dsi_data *dsi, int vc,
2165 WARN_ON(!dsi_bus_is_locked(dsi));
2167 if (dsi->debug_write)
2171 if (FLD_GET(dsi_read_reg(dsi, DSI_VC_CTRL(vc)), 16, 16)) {
2179 dsi_write_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc), r);
2184 static int dsi_vc_send_null(struct dsi_data *dsi, int vc, int channel)
2191 return dsi_vc_send_long(dsi, vc, &msg);
2197 struct dsi_data *dsi = to_dsi_data(dssdev);
2201 r = dsi_vc_send_short(dsi, vc, msg);
2203 r = dsi_vc_send_long(dsi, vc, msg);
2222 if (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) {
2224 dsi_vc_flush_receive_data(dsi, vc);
2231 static int dsi_vc_read_rx_fifo(struct dsi_data *dsi, int vc, u8 *buf,
2239 if (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20) == 0) {
2245 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc));
2246 if (dsi->debug_read)
2259 if (dsi->debug_read)
2276 if (dsi->debug_read)
2295 if (dsi->debug_read)
2308 val = dsi_read_reg(dsi,
2310 if (dsi->debug_read)
2342 struct dsi_data *dsi = to_dsi_data(dssdev);
2346 if (dsi->debug_read)
2349 r = dsi_vc_send_short(dsi, vc, msg);
2357 r = dsi_vc_read_rx_fifo(dsi, vc, msg->rx_buf, msg->rx_len,
2376 struct dsi_data *dsi = to_dsi_data(dssdev);
2379 r = dsi_vc_send_short(dsi, vc, msg);
2387 r = dsi_vc_read_rx_fifo(dsi, vc, msg->rx_buf, msg->rx_len,
2403 static void dsi_set_lp_rx_timeout(struct dsi_data *dsi, unsigned int ticks,
2413 fck = dsi_fclk_rate(dsi);
2415 r = dsi_read_reg(dsi, DSI_TIMING2);
2420 dsi_write_reg(dsi, DSI_TIMING2, r);
2430 static void dsi_set_ta_timeout(struct dsi_data *dsi, unsigned int ticks,
2440 fck = dsi_fclk_rate(dsi);
2442 r = dsi_read_reg(dsi, DSI_TIMING1);
2447 dsi_write_reg(dsi, DSI_TIMING1, r);
2457 static void dsi_set_stop_state_counter(struct dsi_data *dsi, unsigned int ticks,
2467 fck = dsi_fclk_rate(dsi);
2469 r = dsi_read_reg(dsi, DSI_TIMING1);
2474 dsi_write_reg(dsi, DSI_TIMING1, r);
2484 static void dsi_set_hs_tx_timeout(struct dsi_data *dsi, unsigned int ticks,
2494 fck = dsi_get_txbyteclkhs(dsi);
2496 r = dsi_read_reg(dsi, DSI_TIMING2);
2501 dsi_write_reg(dsi, DSI_TIMING2, r);
2511 static void dsi_config_vp_num_line_buffers(struct dsi_data *dsi)
2515 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2516 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt);
2517 const struct videomode *vm = &dsi->vm;
2522 if (dsi->line_buffer_size <= vm->hactive * bpp / 8)
2532 REG_FLD_MOD(dsi, DSI_CTRL, num_line_buffers, 13, 12);
2535 static void dsi_config_vp_sync_events(struct dsi_data *dsi)
2540 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE)
2545 r = dsi_read_reg(dsi, DSI_CTRL);
2553 dsi_write_reg(dsi, DSI_CTRL, r);
2556 static void dsi_config_blanking_modes(struct dsi_data *dsi)
2558 int blanking_mode = dsi->vm_timings.blanking_mode;
2559 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
2560 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
2561 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
2568 r = dsi_read_reg(dsi, DSI_CTRL);
2573 dsi_write_reg(dsi, DSI_CTRL, r);
2638 static void dsi_config_cmd_mode_interleaving(struct dsi_data *dsi)
2646 const struct videomode *vm = &dsi->vm;
2647 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt);
2648 int ndl = dsi->num_lanes_used - 1;
2649 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1;
2656 r = dsi_read_reg(dsi, DSI_CTRL);
2662 r = dsi_read_reg(dsi, DSI_VM_TIMING1);
2667 r = dsi_read_reg(dsi, DSI_CLK_TIMING);
2671 r = dsi_read_reg(dsi, DSI_VM_TIMING7);
2675 r = dsi_read_reg(dsi, DSI_CLK_CTRL);
2679 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
2682 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
2736 r = dsi_read_reg(dsi, DSI_VM_TIMING4);
2740 dsi_write_reg(dsi, DSI_VM_TIMING4, r);
2742 r = dsi_read_reg(dsi, DSI_VM_TIMING5);
2746 dsi_write_reg(dsi, DSI_VM_TIMING5, r);
2748 r = dsi_read_reg(dsi, DSI_VM_TIMING6);
2751 dsi_write_reg(dsi, DSI_VM_TIMING6, r);
2754 static int dsi_proto_config(struct dsi_data *dsi)
2759 dsi_config_tx_fifo(dsi, DSI_FIFO_SIZE_32,
2764 dsi_config_rx_fifo(dsi, DSI_FIFO_SIZE_32,
2770 dsi_set_stop_state_counter(dsi, 0x1000, false, false);
2771 dsi_set_ta_timeout(dsi, 0x1fff, true, true);
2772 dsi_set_lp_rx_timeout(dsi, 0x1fff, true, true);
2773 dsi_set_hs_tx_timeout(dsi, 0x1fff, true, true);
2775 switch (mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt)) {
2790 r = dsi_read_reg(dsi, DSI_CTRL);
2799 if (!(dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC)) {
2805 dsi_write_reg(dsi, DSI_CTRL, r);
2807 dsi_config_vp_num_line_buffers(dsi);
2809 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2810 dsi_config_vp_sync_events(dsi);
2811 dsi_config_blanking_modes(dsi);
2812 dsi_config_cmd_mode_interleaving(dsi);
2815 dsi_vc_initial_config(dsi, 0);
2816 dsi_vc_initial_config(dsi, 1);
2817 dsi_vc_initial_config(dsi, 2);
2818 dsi_vc_initial_config(dsi, 3);
2823 static void dsi_proto_timings(struct dsi_data *dsi)
2832 int ndl = dsi->num_lanes_used - 1;
2835 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
2842 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
2846 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2);
2852 tclk_post = ns2ddr(dsi, 60) + 26;
2863 r = dsi_read_reg(dsi, DSI_CLK_TIMING);
2866 dsi_write_reg(dsi, DSI_CLK_TIMING, r);
2880 dsi_write_reg(dsi, DSI_VM_TIMING7, r);
2885 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2887 int hsa = dsi->vm_timings.hsa;
2888 int hfp = dsi->vm_timings.hfp;
2889 int hbp = dsi->vm_timings.hbp;
2890 int vsa = dsi->vm_timings.vsa;
2891 int vfp = dsi->vm_timings.vfp;
2892 int vbp = dsi->vm_timings.vbp;
2893 int window_sync = dsi->vm_timings.window_sync;
2895 const struct videomode *vm = &dsi->vm;
2896 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt);
2899 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE;
2914 r = dsi_read_reg(dsi, DSI_VM_TIMING1);
2918 dsi_write_reg(dsi, DSI_VM_TIMING1, r);
2920 r = dsi_read_reg(dsi, DSI_VM_TIMING2);
2925 dsi_write_reg(dsi, DSI_VM_TIMING2, r);
2927 r = dsi_read_reg(dsi, DSI_VM_TIMING3);
2930 dsi_write_reg(dsi, DSI_VM_TIMING3, r);
2934 static int dsi_configure_pins(struct dsi_data *dsi,
2949 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
2965 if (dx >= dsi->num_lanes_supported * 2)
2968 if (dy >= dsi->num_lanes_supported * 2)
2988 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
2989 dsi->num_lanes_used = num_lanes;
2994 static int dsi_enable_video_mode(struct dsi_data *dsi, int vc)
2996 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt);
3000 switch (dsi->pix_fmt) {
3017 dsi_if_enable(dsi, false);
3018 dsi_vc_enable(dsi, vc, false);
3021 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), 1, 4, 4);
3023 word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8);
3025 dsi_vc_write_long_header(dsi, vc, dsi->dsidev->channel, data_type,
3028 dsi_vc_enable(dsi, vc, true);
3029 dsi_if_enable(dsi, true);
3034 static void dsi_disable_video_mode(struct dsi_data *dsi, int vc)
3036 dsi_if_enable(dsi, false);
3037 dsi_vc_enable(dsi, vc, false);
3040 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), 0, 4, 4);
3042 dsi_vc_enable(dsi, vc, true);
3043 dsi_if_enable(dsi, true);
3048 struct dsi_data *dsi = to_dsi_data(dssdev);
3051 r = dsi_init_dispc(dsi);
3053 dev_err(dsi->dev, "failed to init dispc!\n");
3057 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3058 r = dsi_enable_video_mode(dsi, vc);
3063 r = dss_mgr_enable(&dsi->output);
3070 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3071 dsi_if_enable(dsi, false);
3072 dsi_vc_enable(dsi, vc, false);
3075 dsi_uninit_dispc(dsi);
3076 dev_err(dsi->dev, "failed to enable DSI encoder!\n");
3082 struct dsi_data *dsi = to_dsi_data(dssdev);
3084 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE)
3085 dsi_disable_video_mode(dsi, vc);
3087 dss_mgr_disable(&dsi->output);
3089 dsi_uninit_dispc(dsi);
3092 static void dsi_update_screen_dispc(struct dsi_data *dsi)
3102 const unsigned vc = dsi->update_vc;
3103 const unsigned int line_buf_size = dsi->line_buffer_size;
3104 u16 w = dsi->vm.hactive;
3105 u16 h = dsi->vm.vactive;
3109 bytespp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt) / 8;
3128 dsi_write_reg(dsi, DSI_VC_TE(vc), l);
3130 dsi_vc_write_long_header(dsi, vc, dsi->dsidev->channel, MIPI_DSI_DCS_LONG_WRITE,
3133 if (dsi->te_enabled)
3137 dsi_write_reg(dsi, DSI_VC_TE(vc), l);
3145 dispc_disable_sidle(dsi->dss->dispc);
3147 dsi_perf_mark_start(dsi);
3149 r = schedule_delayed_work(&dsi->framedone_timeout_work,
3153 dss_mgr_start_update(&dsi->output);
3155 if (dsi->te_enabled) {
3158 REG_FLD_MOD(dsi, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
3160 dsi_vc_send_bta(dsi, vc);
3163 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
3175 static void dsi_handle_framedone(struct dsi_data *dsi, int error)
3178 dispc_enable_sidle(dsi->dss->dispc);
3180 if (dsi->te_enabled) {
3182 REG_FLD_MOD(dsi, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
3185 dsi_bus_unlock(dsi);
3188 dsi_perf_show(dsi, "DISPC");
3193 struct dsi_data *dsi = container_of(work, struct dsi_data,
3204 dsi_handle_framedone(dsi, -ETIMEDOUT);
3209 struct dsi_data *dsi = data;
3216 cancel_delayed_work(&dsi->framedone_timeout_work);
3220 dsi_handle_framedone(dsi, 0);
3223 static int _dsi_update(struct dsi_data *dsi)
3225 dsi_perf_mark_setup(dsi);
3228 dsi->update_bytes = dsi->vm.hactive * dsi->vm.vactive *
3229 mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt) / 8;
3231 dsi_update_screen_dispc(dsi);
3236 static int _dsi_send_nop(struct dsi_data *dsi, int vc, int channel)
3246 WARN_ON(!dsi_bus_is_locked(dsi));
3248 return _omap_dsi_host_transfer(dsi, vc, &msg);
3253 struct dsi_data *dsi = to_dsi_data(dssdev);
3256 dsi_bus_lock(dsi);
3258 if (!dsi->video_enabled) {
3263 if (dsi->vm.hactive == 0 || dsi->vm.vactive == 0) {
3275 r = _dsi_send_nop(dsi, VC_CMD, dsi->dsidev->channel);
3281 dsi->update_vc = vc;
3283 if (dsi->te_enabled && dsi->te_gpio) {
3284 schedule_delayed_work(&dsi->te_timeout_work,
3286 atomic_set(&dsi->do_ext_te_update, 1);
3288 _dsi_update(dsi);
3294 dsi_bus_unlock(dsi);
3305 static int dsi_configure_dispc_clocks(struct dsi_data *dsi)
3311 fck = dsi_get_pll_hsdiv_dispc_rate(dsi);
3313 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
3314 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
3316 r = dispc_calc_clock_rates(dsi->dss->dispc, fck, &dispc_cinfo);
3322 dsi->mgr_config.clock_info = dispc_cinfo;
3327 static int dsi_init_dispc(struct dsi_data *dsi)
3329 enum omap_channel dispc_channel = dsi->output.dispc_channel;
3332 dss_select_lcd_clk_source(dsi->dss, dispc_channel, dsi->module_id == 0 ?
3336 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
3337 r = dss_mgr_register_framedone_handler(&dsi->output,
3338 dsi_framedone_irq_callback, dsi);
3344 dsi->mgr_config.stallmode = true;
3345 dsi->mgr_config.fifohandcheck = true;
3347 dsi->mgr_config.stallmode = false;
3348 dsi->mgr_config.fifohandcheck = false;
3351 r = dsi_configure_dispc_clocks(dsi);
3355 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
3356 dsi->mgr_config.video_port_width =
3357 mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt);
3358 dsi->mgr_config.lcden_sig_polarity = 0;
3360 dss_mgr_set_lcd_config(&dsi->output, &dsi->mgr_config);
3364 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
3365 dss_mgr_unregister_framedone_handler(&dsi->output,
3366 dsi_framedone_irq_callback, dsi);
3368 dss_select_lcd_clk_source(dsi->dss, dispc_channel, DSS_CLK_SRC_FCK);
3372 static void dsi_uninit_dispc(struct dsi_data *dsi)
3374 enum omap_channel dispc_channel = dsi->output.dispc_channel;
3376 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
3377 dss_mgr_unregister_framedone_handler(&dsi->output,
3378 dsi_framedone_irq_callback, dsi);
3380 dss_select_lcd_clk_source(dsi->dss, dispc_channel, DSS_CLK_SRC_FCK);
3383 static int dsi_configure_dsi_clocks(struct dsi_data *dsi)
3388 cinfo = dsi->user_dsi_cinfo;
3390 r = dss_pll_set_config(&dsi->pll, &cinfo);
3392 DSSERR("Failed to set dsi clocks\n");
3399 static void dsi_setup_dsi_vcs(struct dsi_data *dsi)
3402 REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_CMD), 0, 9, 9); /* LP */
3404 REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_CMD), 0, 1, 1); /* SOURCE_L4 */
3405 dsi->vc[VC_CMD].source = DSI_VC_SOURCE_L4;
3408 REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_VIDEO), 1, 9, 9); /* HS */
3410 REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_VIDEO), 1, 1, 1); /* SOURCE_VP */
3411 dsi->vc[VC_VIDEO].source = DSI_VC_SOURCE_VP;
3413 if ((dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC) &&
3414 !(dsi->dsidev->mode_flags & MIPI_DSI_MODE_VIDEO))
3415 REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_VIDEO), 1, 30, 30); /* DCS_CMD_ENABLE */
3417 dsi_vc_enable(dsi, VC_CMD, 1);
3418 dsi_vc_enable(dsi, VC_VIDEO, 1);
3420 dsi_if_enable(dsi, 1);
3422 dsi_force_tx_stop_mode_io(dsi);
3425 if (!(dsi->dsidev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
3426 dsi_vc_send_null(dsi, VC_CMD, dsi->dsidev->channel);
3429 static int dsi_init_dsi(struct dsi_data *dsi)
3433 r = dss_pll_enable(&dsi->pll);
3437 r = dsi_configure_dsi_clocks(dsi);
3441 dss_select_dsi_clk_source(dsi->dss, dsi->module_id,
3442 dsi->module_id == 0 ?
3447 if (!dsi->vdds_dsi_enabled) {
3448 r = regulator_enable(dsi->vdds_dsi_reg);
3452 dsi->vdds_dsi_enabled = true;
3455 r = dsi_cio_init(dsi);
3459 _dsi_print_reset_status(dsi);
3461 dsi_proto_timings(dsi);
3462 dsi_set_lp_clk_divisor(dsi);
3465 _dsi_print_reset_status(dsi);
3467 r = dsi_proto_config(dsi);
3471 dsi_setup_dsi_vcs(dsi);
3475 dsi_cio_uninit(dsi);
3477 regulator_disable(dsi->vdds_dsi_reg);
3478 dsi->vdds_dsi_enabled = false;
3480 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK);
3482 dss_pll_disable(&dsi->pll);
3487 static void dsi_uninit_dsi(struct dsi_data *dsi)
3490 dsi_if_enable(dsi, 0);
3491 dsi_vc_enable(dsi, 0, 0);
3492 dsi_vc_enable(dsi, 1, 0);
3493 dsi_vc_enable(dsi, 2, 0);
3494 dsi_vc_enable(dsi, 3, 0);
3496 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK);
3497 dsi_cio_uninit(dsi);
3498 dss_pll_disable(&dsi->pll);
3500 regulator_disable(dsi->vdds_dsi_reg);
3501 dsi->vdds_dsi_enabled = false;
3504 static void dsi_enable(struct dsi_data *dsi)
3508 WARN_ON(!dsi_bus_is_locked(dsi));
3510 if (WARN_ON(dsi->iface_enabled))
3513 mutex_lock(&dsi->lock);
3515 r = dsi_runtime_get(dsi);
3519 _dsi_initialize_irq(dsi);
3521 r = dsi_init_dsi(dsi);
3525 dsi->iface_enabled = true;
3527 mutex_unlock(&dsi->lock);
3532 dsi_runtime_put(dsi);
3534 mutex_unlock(&dsi->lock);
3538 static void dsi_disable(struct dsi_data *dsi)
3540 WARN_ON(!dsi_bus_is_locked(dsi));
3542 if (WARN_ON(!dsi->iface_enabled))
3545 mutex_lock(&dsi->lock);
3547 dsi_sync_vc(dsi, 0);
3548 dsi_sync_vc(dsi, 1);
3549 dsi_sync_vc(dsi, 2);
3550 dsi_sync_vc(dsi, 3);
3552 dsi_uninit_dsi(dsi);
3554 dsi_runtime_put(dsi);
3556 dsi->iface_enabled = false;
3558 mutex_unlock(&dsi->lock);
3561 static int dsi_enable_te(struct dsi_data *dsi, bool enable)
3563 dsi->te_enabled = enable;
3565 if (dsi->te_gpio) {
3567 enable_irq(dsi->te_irq);
3569 disable_irq(dsi->te_irq);
3690 return dispc_div_calc(ctx->dsi->dss->dispc, dispc,
3699 struct dsi_data *dsi = ctx->dsi;
3707 dsi->data->max_fck_freq,
3711 static bool dsi_cm_calc(struct dsi_data *dsi,
3720 clkin = clk_get_rate(dsi->pll.clkin);
3722 ndl = dsi->num_lanes_used - 1;
3735 ctx->dsi = dsi;
3736 ctx->pll = &dsi->pll;
3752 struct dsi_data *dsi = ctx->dsi;
3755 int ndl = dsi->num_lanes_used - 1;
3792 if (dsi->line_buffer_size < xres * bitspp / 8) {
3963 print_dsi_vm("dsi ", &ctx->dsi_vm);
3990 return dispc_div_calc(ctx->dsi->dss->dispc, dispc,
3999 struct dsi_data *dsi = ctx->dsi;
4007 dsi->data->max_fck_freq,
4011 static bool dsi_vm_calc(struct dsi_data *dsi,
4019 int ndl = dsi->num_lanes_used - 1;
4023 clkin = clk_get_rate(dsi->pll.clkin);
4026 ctx->dsi = dsi;
4027 ctx->pll = &dsi->pll;
4055 struct dsi_data *dsi = to_dsi_data(dssdev);
4057 return dsi->mode == OMAP_DSS_DSI_VIDEO_MODE;
4060 static int __dsi_calc_config(struct dsi_data *dsi,
4064 struct omap_dss_dsi_config cfg = dsi->config;
4072 cfg.mode = dsi->mode;
4073 cfg.pixel_format = dsi->pix_fmt;
4075 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE)
4076 ok = dsi_vm_calc(dsi, &cfg, ctx);
4078 ok = dsi_cm_calc(dsi, &cfg, ctx);
4083 dsi_pll_calc_dsi_fck(dsi, &ctx->dsi_cinfo);
4096 struct dsi_data *dsi = to_dsi_data(dssdev);
4100 mutex_lock(&dsi->lock);
4102 r = __dsi_calc_config(dsi, mode, &ctx);
4108 dsi->user_lp_cinfo = ctx.lp_cinfo;
4109 dsi->user_dsi_cinfo = ctx.dsi_cinfo;
4110 dsi->user_dispc_cinfo = ctx.dispc_cinfo;
4112 dsi->vm = ctx.vm;
4118 dsi->vm.flags &= ~DISPLAY_FLAGS_INTERLACED;
4119 dsi->vm.flags &= ~DISPLAY_FLAGS_HSYNC_LOW;
4120 dsi->vm.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
4121 dsi->vm.flags &= ~DISPLAY_FLAGS_VSYNC_LOW;
4122 dsi->vm.flags |= DISPLAY_FLAGS_VSYNC_HIGH;
4128 dsi->vm.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE;
4129 dsi->vm.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE;
4130 dsi->vm.flags &= ~DISPLAY_FLAGS_DE_LOW;
4131 dsi->vm.flags |= DISPLAY_FLAGS_DE_HIGH;
4132 dsi->vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE;
4133 dsi->vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE;
4135 dss_mgr_set_timings(&dsi->output, &dsi->vm);
4137 dsi->vm_timings = ctx.dsi_vm;
4139 mutex_unlock(&dsi->lock);
4143 mutex_unlock(&dsi->lock);
4154 static enum omap_channel dsi_get_dispc_channel(struct dsi_data *dsi)
4156 switch (dsi->data->model) {
4161 switch (dsi->module_id) {
4172 switch (dsi->module_id) {
4188 static ssize_t _omap_dsi_host_transfer(struct dsi_data *dsi, int vc,
4191 struct omap_dss_device *dssdev = &dsi->output;
4229 dsi_enable_te(dsi, false);
4231 dsi_enable_te(dsi, true);
4240 struct dsi_data *dsi = host_to_omap(host);
4244 dsi_bus_lock(dsi);
4246 if (!dsi->iface_enabled) {
4247 dsi_enable(dsi);
4248 schedule_delayed_work(&dsi->dsi_disable_work, msecs_to_jiffies(2000));
4251 r = _omap_dsi_host_transfer(dsi, vc, msg);
4253 dsi_bus_unlock(dsi);
4258 static int dsi_get_clocks(struct dsi_data *dsi)
4262 clk = devm_clk_get(dsi->dev, "fck");
4268 dsi->dss_clk = clk;
4280 struct dsi_data *dsi = (struct dsi_data *)dev_id;
4283 old = atomic_cmpxchg(&dsi->do_ext_te_update, 1, 0);
4285 cancel_delayed_work(&dsi->te_timeout_work);
4286 _dsi_update(dsi);
4294 struct dsi_data *dsi =
4298 old = atomic_cmpxchg(&dsi->do_ext_te_update, 1, 0);
4300 dev_err(dsi->dev, "TE not received for 250ms!\n");
4301 _dsi_update(dsi);
4305 static int omap_dsi_register_te_irq(struct dsi_data *dsi,
4311 dsi->te_gpio = gpiod_get(&client->dev, "te-gpios", GPIOD_IN);
4312 if (IS_ERR(dsi->te_gpio)) {
4313 err = PTR_ERR(dsi->te_gpio);
4316 dsi->te_gpio = NULL;
4320 dev_err(dsi->dev, "Could not get TE gpio: %d\n", err);
4324 te_irq = gpiod_to_irq(dsi->te_gpio);
4326 gpiod_put(dsi->te_gpio);
4327 dsi->te_gpio = NULL;
4331 dsi->te_irq = te_irq;
4337 "TE", dsi);
4339 dev_err(dsi->dev, "request irq failed with %d\n", err);
4340 gpiod_put(dsi->te_gpio);
4341 dsi->te_gpio = NULL;
4345 INIT_DEFERRABLE_WORK(&dsi->te_timeout_work,
4348 dev_dbg(dsi->dev, "Using GPIO TE\n");
4353 static void omap_dsi_unregister_te_irq(struct dsi_data *dsi)
4355 if (dsi->te_gpio) {
4356 free_irq(dsi->te_irq, dsi);
4357 cancel_delayed_work(&dsi->te_timeout_work);
4358 gpiod_put(dsi->te_gpio);
4359 dsi->te_gpio = NULL;
4366 struct dsi_data *dsi = host_to_omap(host);
4369 if (dsi->dsidev) {
4370 DSSERR("dsi client already attached\n");
4379 atomic_set(&dsi->do_ext_te_update, 0);
4382 dsi->mode = OMAP_DSS_DSI_VIDEO_MODE;
4384 r = omap_dsi_register_te_irq(dsi, client);
4388 dsi->mode = OMAP_DSS_DSI_CMD_MODE;
4391 dsi->dsidev = client;
4392 dsi->pix_fmt = client->format;
4394 dsi->config.hs_clk_min = 150000000; // TODO: get from client?
4395 dsi->config.hs_clk_max = client->hs_rate;
4396 dsi->config.lp_clk_min = 7000000; // TODO: get from client?
4397 dsi->config.lp_clk_max = client->lp_rate;
4400 dsi->config.trans_mode = OMAP_DSS_DSI_BURST_MODE;
4402 dsi->config.trans_mode = OMAP_DSS_DSI_PULSE_MODE;
4404 dsi->config.trans_mode = OMAP_DSS_DSI_EVENT_MODE;
4412 struct dsi_data *dsi = host_to_omap(host);
4414 if (WARN_ON(dsi->dsidev != client))
4417 cancel_delayed_work_sync(&dsi->dsi_disable_work);
4419 dsi_bus_lock(dsi);
4421 if (dsi->iface_enabled)
4422 dsi_disable(dsi);
4424 dsi_bus_unlock(dsi);
4426 omap_dsi_unregister_te_irq(dsi);
4427 dsi->dsidev = NULL;
4528 static int dsi_init_pll_data(struct dss_device *dss, struct dsi_data *dsi)
4530 struct dss_pll *pll = &dsi->pll;
4534 clk = devm_clk_get(dsi->dev, "sys_clk");
4540 pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1";
4541 pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2;
4543 pll->base = dsi->pll_base;
4544 pll->hw = dsi->data->pll_hw;
4561 struct dsi_data *dsi = dev_get_drvdata(dev);
4566 dsi->dss = dss;
4568 dsi_init_pll_data(dss, dsi);
4570 r = dsi_runtime_get(dsi);
4574 rev = dsi_read_reg(dsi, DSI_REVISION);
4578 dsi->line_buffer_size = dsi_get_line_buf_size(dsi);
4580 dsi_runtime_put(dsi);
4582 snprintf(name, sizeof(name), "dsi%u_regs", dsi->module_id + 1);
4583 dsi->debugfs.regs = dss_debugfs_create_file(dss, name,
4584 dsi_dump_dsi_regs, dsi);
4586 snprintf(name, sizeof(name), "dsi%u_irqs", dsi->module_id + 1);
4587 dsi->debugfs.irqs = dss_debugfs_create_file(dss, name,
4588 dsi_dump_dsi_irqs, dsi);
4590 snprintf(name, sizeof(name), "dsi%u_clks", dsi->module_id + 1);
4591 dsi->debugfs.clks = dss_debugfs_create_file(dss, name,
4592 dsi_dump_dsi_clocks, dsi);
4599 struct dsi_data *dsi = dev_get_drvdata(dev);
4601 dss_debugfs_remove_file(dsi->debugfs.clks);
4602 dss_debugfs_remove_file(dsi->debugfs.irqs);
4603 dss_debugfs_remove_file(dsi->debugfs.regs);
4605 WARN_ON(dsi->scp_clk_refcount > 0);
4607 dss_pll_unregister(&dsi->pll);
4622 struct dsi_data *dsi = drm_bridge_to_dsi(bridge);
4627 return drm_bridge_attach(bridge->encoder, dsi->output.next_bridge,
4636 struct dsi_data *dsi = drm_bridge_to_dsi(bridge);
4640 mutex_lock(&dsi->lock);
4641 r = __dsi_calc_config(dsi, mode, &ctx);
4642 mutex_unlock(&dsi->lock);
4651 struct dsi_data *dsi = drm_bridge_to_dsi(bridge);
4653 dsi_set_config(&dsi->output, adjusted_mode);
4658 struct dsi_data *dsi = drm_bridge_to_dsi(bridge);
4659 struct omap_dss_device *dssdev = &dsi->output;
4661 cancel_delayed_work_sync(&dsi->dsi_disable_work);
4663 dsi_bus_lock(dsi);
4665 if (!dsi->iface_enabled)
4666 dsi_enable(dsi);
4670 dsi->video_enabled = true;
4672 dsi_bus_unlock(dsi);
4677 struct dsi_data *dsi = drm_bridge_to_dsi(bridge);
4678 struct omap_dss_device *dssdev = &dsi->output;
4680 cancel_delayed_work_sync(&dsi->dsi_disable_work);
4682 dsi_bus_lock(dsi);
4684 dsi->video_enabled = false;
4688 dsi_disable(dsi);
4690 dsi_bus_unlock(dsi);
4701 static void dsi_bridge_init(struct dsi_data *dsi)
4703 dsi->bridge.funcs = &dsi_bridge_funcs;
4704 dsi->bridge.of_node = dsi->host.dev->of_node;
4705 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
4707 drm_bridge_add(&dsi->bridge);
4710 static void dsi_bridge_cleanup(struct dsi_data *dsi)
4712 drm_bridge_remove(&dsi->bridge);
4719 static int dsi_init_output(struct dsi_data *dsi)
4721 struct omap_dss_device *out = &dsi->output;
4724 dsi_bridge_init(dsi);
4726 out->dev = dsi->dev;
4727 out->id = dsi->module_id == 0 ?
4731 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
4732 out->dispc_channel = dsi_get_dispc_channel(dsi);
4739 r = omapdss_device_init_output(out, &dsi->bridge);
4741 dsi_bridge_cleanup(dsi);
4750 static void dsi_uninit_output(struct dsi_data *dsi)
4752 struct omap_dss_device *out = &dsi->output;
4756 dsi_bridge_cleanup(dsi);
4759 static int dsi_probe_of(struct dsi_data *dsi)
4761 struct device_node *node = dsi->dev->of_node;
4774 dev_err(dsi->dev, "failed to find lane data\n");
4782 num_pins > dsi->num_lanes_supported * 2) {
4783 dev_err(dsi->dev, "bad number of lanes\n");
4790 dev_err(dsi->dev, "failed to read lane data\n");
4794 r = dsi_configure_pins(dsi, num_pins, lane_arr);
4796 dev_err(dsi->dev, "failed to configure pins");
4862 { .compatible = "ti,omap3-dsi", .data = &dsi_of_data_omap36xx, },
4863 { .compatible = "ti,omap4-dsi", .data = &dsi_of_data_omap4, },
4864 { .compatible = "ti,omap5-dsi", .data = &dsi_of_data_omap5, },
4876 struct dsi_data *dsi = container_of(work, struct dsi_data, dsi_disable_work.work);
4878 dsi_bus_lock(dsi);
4880 if (dsi->iface_enabled && !dsi->video_enabled)
4881 dsi_disable(dsi);
4883 dsi_bus_unlock(dsi);
4891 struct dsi_data *dsi;
4896 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
4897 if (!dsi)
4900 dsi->dev = dev;
4901 dev_set_drvdata(dev, dsi);
4903 spin_lock_init(&dsi->irq_lock);
4904 spin_lock_init(&dsi->errors_lock);
4905 dsi->errors = 0;
4908 spin_lock_init(&dsi->irq_stats_lock);
4909 dsi->irq_stats.last_reset = jiffies;
4912 mutex_init(&dsi->lock);
4913 sema_init(&dsi->bus_lock, 1);
4915 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
4918 INIT_DEFERRABLE_WORK(&dsi->dsi_disable_work, omap_dsi_disable_work_callback);
4921 timer_setup(&dsi->te_timer, dsi_te_timeout, 0);
4925 dsi->proto_base = devm_ioremap_resource(dev, dsi_mem);
4926 if (IS_ERR(dsi->proto_base))
4927 return PTR_ERR(dsi->proto_base);
4929 dsi->phy_base = devm_platform_ioremap_resource_byname(pdev, "phy");
4930 if (IS_ERR(dsi->phy_base))
4931 return PTR_ERR(dsi->phy_base);
4933 dsi->pll_base = devm_platform_ioremap_resource_byname(pdev, "pll");
4934 if (IS_ERR(dsi->pll_base))
4935 return PTR_ERR(dsi->pll_base);
4937 dsi->irq = platform_get_irq(pdev, 0);
4938 if (dsi->irq < 0) {
4943 r = devm_request_irq(dev, dsi->irq, omap_dsi_irq_handler,
4944 IRQF_SHARED, dev_name(dev), dsi);
4950 dsi->vdds_dsi_reg = devm_regulator_get(dev, "vdd");
4951 if (IS_ERR(dsi->vdds_dsi_reg)) {
4952 if (PTR_ERR(dsi->vdds_dsi_reg) != -EPROBE_DEFER)
4954 return PTR_ERR(dsi->vdds_dsi_reg);
4959 dsi->data = soc->data;
4961 dsi->data = of_match_node(dsi_of_match, dev->of_node)->data;
4963 d = dsi->data->modules;
4972 dsi->module_id = d->id;
4974 if (dsi->data->model == DSI_MODEL_OMAP4 ||
4975 dsi->data->model == DSI_MODEL_OMAP5) {
4983 dsi->data->model == DSI_MODEL_OMAP4 ?
4988 dsi->syscon = syscon_node_to_regmap(np);
4993 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++)
4994 dsi->vc[i].source = DSI_VC_SOURCE_L4;
4996 r = dsi_get_clocks(dsi);
5004 if (dsi->data->quirks & DSI_QUIRK_GNQ) {
5005 dsi_runtime_get(dsi);
5007 dsi->num_lanes_supported = 1 + REG_GET(dsi, DSI_GNQ, 11, 9);
5008 dsi_runtime_put(dsi);
5010 dsi->num_lanes_supported = 3;
5013 dsi->host.ops = &omap_dsi_host_ops;
5014 dsi->host.dev = &pdev->dev;
5016 r = dsi_probe_of(dsi);
5022 r = mipi_dsi_host_register(&dsi->host);
5028 r = dsi_init_output(dsi);
5039 dsi_uninit_output(dsi);
5041 mipi_dsi_host_unregister(&dsi->host);
5049 struct dsi_data *dsi = platform_get_drvdata(pdev);
5053 dsi_uninit_output(dsi);
5055 mipi_dsi_host_unregister(&dsi->host);
5059 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) {
5060 regulator_disable(dsi->vdds_dsi_reg);
5061 dsi->vdds_dsi_enabled = false;
5067 struct dsi_data *dsi = dev_get_drvdata(dev);
5069 dsi->is_enabled = false;
5073 synchronize_irq(dsi->irq);
5080 struct dsi_data *dsi = dev_get_drvdata(dev);
5082 dsi->is_enabled = true;