Lines Matching refs:data
130 static void dsi_completion_handler(void *data, u32 mask)
132 complete((struct completion *)data);
734 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) {
831 unsigned int lpdiv_max = dsi->data->max_pll_lpdiv;
881 if ((dsi->data->quirks & DSI_QUIRK_PLL_PWR_BUG) &&
907 max_dsi_fck = dsi->data->max_fck_freq;
1256 if (!(dsi->data->quirks & DSI_QUIRK_GNQ))
1408 if (dsi->data->quirks & DSI_QUIRK_PHY_DCC) {
1429 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC)
1544 if (dsi->data->model == DSI_MODEL_OMAP4)
1546 if (dsi->data->model == DSI_MODEL_OMAP5)
1553 if (dsi->data->model == DSI_MODEL_OMAP4)
1555 else if (dsi->data->model == DSI_MODEL_OMAP5)
1733 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
1736 (struct dsi_packet_sent_handler_data *) data;
1783 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
1786 (struct dsi_packet_sent_handler_data *) data;
1885 if (dsi->data->quirks & DSI_QUIRK_VC_OCP_WIDTH)
2007 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2223 DSSERR("rx fifo not empty after write, dumping data:\n");
2258 u8 data = FLD_GET(val, 15, 8);
2262 "DCS", data);
2269 buf[0] = data;
2275 u16 data = FLD_GET(val, 23, 8);
2279 "DCS", data);
2286 buf[0] = data & 0xff;
2287 buf[1] = (data >> 8) & 0xff;
2578 * results in maximum transition time for data and clock lanes to enter and
2580 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
2581 * clock cycles that can be used to interleave command mode data in HS so that
2591 * time of data lanes only, if it isn't set, we need to consider HS
2592 * transition time of both data and clock lanes. HS transition time
2610 * results in maximum transition time for data lanes to enter and exit LP mode.
2611 * Hence, this is the scenario where the least amount of command mode data can
2622 int lp_inter; /* cmd mode data that can be interleaved, in bytes */
2799 if (!(dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC)) {
3207 static void dsi_framedone_irq_callback(void *data)
3209 struct dsi_data *dsi = data;
3213 * and is sending the data.
3413 if ((dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC) &&
3662 unsigned long pck, void *data)
3664 struct dsi_clk_calc_ctx *ctx = data;
3683 void *data)
3685 struct dsi_clk_calc_ctx *ctx = data;
3696 unsigned long clkdco, void *data)
3698 struct dsi_clk_calc_ctx *ctx = data;
3707 dsi->data->max_fck_freq,
3949 unsigned long pck, void *data)
3951 struct dsi_clk_calc_ctx *ctx = data;
3972 void *data)
3974 struct dsi_clk_calc_ctx *ctx = data;
3996 unsigned long clkdco, void *data)
3998 struct dsi_clk_calc_ctx *ctx = data;
4007 dsi->data->max_fck_freq,
4156 switch (dsi->data->model) {
4544 pll->hw = dsi->data->pll_hw;
4558 static int dsi_bind(struct device *dev, struct device *master, void *data)
4597 static void dsi_unbind(struct device *dev, struct device *master, void *data)
4774 dev_err(dsi->dev, "failed to find lane data\n");
4790 dev_err(dsi->dev, "failed to read lane data\n");
4862 { .compatible = "ti,omap3-dsi", .data = &dsi_of_data_omap36xx, },
4863 { .compatible = "ti,omap4-dsi", .data = &dsi_of_data_omap4, },
4864 { .compatible = "ti,omap5-dsi", .data = &dsi_of_data_omap5, },
4869 { .machine = "OMAP3[45]*", .data = &dsi_of_data_omap34xx },
4870 { .machine = "AM35*", .data = &dsi_of_data_omap34xx },
4959 dsi->data = soc->data;
4961 dsi->data = of_match_node(dsi_of_match, dev->of_node)->data;
4963 d = dsi->data->modules;
4974 if (dsi->data->model == DSI_MODEL_OMAP4 ||
4975 dsi->data->model == DSI_MODEL_OMAP5) {
4983 dsi->data->model == DSI_MODEL_OMAP4 ?
5003 * of data to 3 by default */
5004 if (dsi->data->quirks & DSI_QUIRK_GNQ) {
5018 DSSERR("Invalid DSI DT data\n");