Lines Matching refs:plane
176 /* maps which plane is using a fifo. fifo-id -> plane-id */
352 enum omap_plane_id plane);
354 enum omap_plane_id plane);
736 enum omap_plane_id plane = OMAP_DSS_WB;
739 enable = REG_GET(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
754 enum omap_plane_id plane, int reg,
757 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H(plane, reg), value);
761 enum omap_plane_id plane, int reg,
764 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV(plane, reg), value);
768 enum omap_plane_id plane, int reg,
771 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V(plane, reg), value);
775 enum omap_plane_id plane, int reg,
778 BUG_ON(plane == OMAP_DSS_GFX);
780 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H2(plane, reg), value);
784 enum omap_plane_id plane, int reg,
787 BUG_ON(plane == OMAP_DSS_GFX);
789 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
793 enum omap_plane_id plane, int reg,
796 BUG_ON(plane == OMAP_DSS_GFX);
798 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V2(plane, reg), value);
802 enum omap_plane_id plane, int fir_hinc,
831 dispc_ovl_write_firh_reg(dispc, plane, i, h);
832 dispc_ovl_write_firhv_reg(dispc, plane, i, hv);
834 dispc_ovl_write_firh2_reg(dispc, plane, i, h);
835 dispc_ovl_write_firhv2_reg(dispc, plane, i, hv);
846 dispc_ovl_write_firv_reg(dispc, plane, i, v);
848 dispc_ovl_write_firv2_reg(dispc, plane, i, v);
859 enum omap_plane_id plane,
864 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
865 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
866 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
867 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
868 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
870 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
908 enum omap_plane_id plane,
930 dispc_ovl_write_color_conv_coef(dispc, plane, csc);
934 enum omap_plane_id plane, u32 paddr)
936 dispc_write_reg(dispc, DISPC_OVL_BA0(plane), paddr);
940 enum omap_plane_id plane, u32 paddr)
942 dispc_write_reg(dispc, DISPC_OVL_BA1(plane), paddr);
946 enum omap_plane_id plane, u32 paddr)
948 dispc_write_reg(dispc, DISPC_OVL_BA0_UV(plane), paddr);
952 enum omap_plane_id plane, u32 paddr)
954 dispc_write_reg(dispc, DISPC_OVL_BA1_UV(plane), paddr);
958 enum omap_plane_id plane,
968 dispc_write_reg(dispc, DISPC_OVL_POSITION(plane), val);
972 enum omap_plane_id plane, int width,
977 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
978 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val);
980 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val);
984 enum omap_plane_id plane, int width,
989 BUG_ON(plane == OMAP_DSS_GFX);
993 if (plane == OMAP_DSS_WB)
994 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val);
996 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val);
1000 enum omap_plane_id plane,
1006 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
1021 enum omap_plane_id plane,
1028 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
1032 enum omap_plane_id plane,
1042 shift = shifts[plane];
1047 enum omap_plane_id plane, s32 inc)
1049 dispc_write_reg(dispc, DISPC_OVL_PIXEL_INC(plane), inc);
1053 enum omap_plane_id plane, s32 inc)
1055 dispc_write_reg(dispc, DISPC_OVL_ROW_INC(plane), inc);
1059 enum omap_plane_id plane, u32 fourcc)
1062 if (plane != OMAP_DSS_GFX) {
1128 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
1132 enum omap_plane_id plane,
1139 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
1141 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
1145 enum omap_plane_id plane,
1152 switch (plane) {
1166 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1204 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val);
1208 enum omap_plane_id plane)
1213 switch (plane) {
1227 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1249 enum omap_plane_id plane,
1255 shift = shifts[plane];
1256 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), burst_size,
1273 enum omap_plane_id plane)
1280 enum omap_plane_id plane, u32 fourcc)
1285 modes = dispc->feat->supported_color_modes[plane];
1296 enum omap_plane_id plane)
1298 return dispc->feat->supported_color_modes[plane];
1332 enum omap_plane_id plane, bool enable)
1336 BUG_ON(plane == OMAP_DSS_GFX);
1338 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1340 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val);
1344 enum omap_plane_id plane,
1354 shift = shifts[plane];
1355 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1398 * giving GFX plane a larger fifo. WB but should work fine with a
1445 enum omap_plane_id plane)
1451 if (dispc->fifo_assignment[fifo] == plane)
1459 enum omap_plane_id plane,
1479 plane,
1480 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane),
1482 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane),
1486 dispc_write_reg(dispc, DISPC_OVL_FIFO_THRESHOLD(plane),
1496 dispc->feat->set_max_preload && plane != OMAP_DSS_WB)
1497 dispc_write_reg(dispc, DISPC_OVL_PRELOAD(plane),
1513 enum omap_plane_id plane,
1525 burst_size = dispc_ovl_get_burst_size(dispc, plane);
1526 ovl_fifo_size = dispc_ovl_get_fifo_size(dispc, plane);
1545 } else if (plane == OMAP_DSS_WB) {
1560 enum omap_plane_id plane, bool enable)
1564 if (plane == OMAP_DSS_GFX)
1569 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1573 enum omap_plane_id plane,
1576 dispc_write_reg(dispc, DISPC_OVL_MFLAG_THRESHOLD(plane),
1638 enum omap_plane_id plane,
1654 dispc_write_reg(dispc, DISPC_OVL_FIR(plane), val);
1657 dispc_write_reg(dispc, DISPC_OVL_FIR2(plane), val);
1662 enum omap_plane_id plane, int haccu,
1676 dispc_write_reg(dispc, DISPC_OVL_ACCU0(plane), val);
1680 enum omap_plane_id plane, int haccu,
1694 dispc_write_reg(dispc, DISPC_OVL_ACCU1(plane), val);
1698 enum omap_plane_id plane, int haccu,
1704 dispc_write_reg(dispc, DISPC_OVL_ACCU2_0(plane), val);
1708 enum omap_plane_id plane, int haccu,
1714 dispc_write_reg(dispc, DISPC_OVL_ACCU2_1(plane), val);
1718 enum omap_plane_id plane,
1729 dispc_ovl_set_scale_coef(dispc, plane, fir_hinc, fir_vinc, five_taps,
1731 dispc_ovl_set_fir(dispc, plane, fir_hinc, fir_vinc, color_comp);
1735 enum omap_plane_id plane,
1819 dispc_ovl_set_vid_accu2_0(dispc, plane, h_accu2_0, v_accu2_0);
1820 dispc_ovl_set_vid_accu2_1(dispc, plane, h_accu2_1, v_accu2_1);
1824 enum omap_plane_id plane,
1835 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height,
1838 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1859 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l);
1874 dispc_ovl_set_vid_accu0(dispc, plane, 0, accu0);
1875 dispc_ovl_set_vid_accu1(dispc, plane, 0, accu1);
1879 enum omap_plane_id plane,
1888 bool chroma_upscale = plane != OMAP_DSS_WB;
1898 if (plane != OMAP_DSS_WB)
1899 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane),
1904 dispc_ovl_set_accu_uv(dispc, plane, orig_width, orig_height, out_width,
1947 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height,
1951 if (plane != OMAP_DSS_WB)
1952 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane),
1956 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1958 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1962 enum omap_plane_id plane,
1969 BUG_ON(plane == OMAP_DSS_GFX);
1971 dispc_ovl_set_scaling_common(dispc, plane, orig_width, orig_height,
1975 dispc_ovl_set_scaling_uv(dispc, plane, orig_width, orig_height,
1981 enum omap_plane_id plane, u8 rotation,
2037 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
2039 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane),
2042 if (dispc_ovl_color_mode_supported(dispc, plane, DRM_FORMAT_NV12)) {
2049 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane),
2487 enum omap_overlay_caps dispc_ovl_get_caps(struct dispc_device *dispc, enum omap_plane_id plane)
2489 return dispc->feat->overlay_caps[plane];
2496 enum omap_plane_id plane,
2529 if (plane == OMAP_DSS_WB) {
2611 enum omap_plane_id plane,
2637 unsigned long pclk = dispc_plane_pclk_rate(dispc, plane);
2638 unsigned long lclk = dispc_plane_lclk_rate(dispc, plane);
2644 if (plane == OMAP_DSS_WB)
2658 if (plane != OMAP_DSS_WB) {
2673 if (!dispc_ovl_color_mode_supported(dispc, plane, fourcc))
2676 r = dispc_ovl_calc_scaling(dispc, plane, pclk, lclk, caps, vm, in_width,
2724 if (plane == OMAP_DSS_WB)
2738 dispc_ovl_set_color_mode(dispc, plane, fourcc);
2740 dispc_ovl_configure_burst_type(dispc, plane, rotation_type);
2745 dispc_ovl_set_ba0(dispc, plane, paddr + offset0);
2746 dispc_ovl_set_ba1(dispc, plane, paddr + offset1);
2749 dispc_ovl_set_ba0_uv(dispc, plane, p_uv_addr + offset0);
2750 dispc_ovl_set_ba1_uv(dispc, plane, p_uv_addr + offset1);
2756 dispc_ovl_set_row_inc(dispc, plane, row_inc);
2757 dispc_ovl_set_pix_inc(dispc, plane, pix_inc);
2762 dispc_ovl_set_pos(dispc, plane, caps, pos_x, pos_y);
2764 dispc_ovl_set_input_size(dispc, plane, in_width, in_height);
2767 dispc_ovl_set_scaling(dispc, plane, in_width, in_height,
2770 dispc_ovl_set_output_size(dispc, plane, out_width, out_height);
2771 dispc_ovl_set_vid_color_conv(dispc, plane, cconv);
2773 if (plane != OMAP_DSS_WB)
2774 dispc_ovl_set_csc(dispc, plane, color_encoding, color_range);
2777 dispc_ovl_set_rotation_attrs(dispc, plane, rotation, rotation_type,
2780 dispc_ovl_set_zorder(dispc, plane, caps, zorder);
2781 dispc_ovl_set_pre_mult_alpha(dispc, plane, caps, pre_mult_alpha);
2782 dispc_ovl_setup_global_alpha(dispc, plane, caps, global_alpha);
2784 dispc_ovl_enable_replication(dispc, plane, caps, replication);
2790 enum omap_plane_id plane,
2796 enum omap_overlay_caps caps = dispc->feat->overlay_caps[plane];
2801 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2805 dispc_ovl_set_channel_out(dispc, plane, channel);
2807 r = dispc_ovl_setup_common(dispc, plane, caps, oi->paddr, oi->p_uv_addr,
2824 enum omap_plane_id plane = OMAP_DSS_WB;
2841 r = dispc_ovl_setup_common(dispc, plane, caps, wi->paddr, wi->p_uv_addr,
2867 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
2875 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l);
2879 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);
2895 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
2907 enum omap_plane_id plane, bool enable)
2909 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2911 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
3376 enum omap_plane_id plane)
3380 if (plane == OMAP_DSS_WB)
3383 channel = dispc_ovl_get_channel_out(dispc, plane);
3389 enum omap_plane_id plane)
3393 if (plane == OMAP_DSS_WB)
3396 channel = dispc_ovl_get_channel_out(dispc, plane);
3614 #define DISPC_REG(plane, name, i) name(plane, i)
3615 #define DUMPREG(dispc, plane, name, i) \
3616 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3617 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3618 dispc_read_reg(dispc, DISPC_REG(plane, name, i)))
4568 * For gamma tables to work on LCD1 the GFX plane has to be used at
4570 * sets up a minimal LCD setup with GFX plane and waits for one
4684 /* Setup and enable GFX plane */