Lines Matching defs:val
53 #define REG_FLD_MOD(dispc, idx, val, start, end) \
55 FLD_MOD(dispc_read_reg(dispc, idx), val, start, end))
356 static inline void dispc_write_reg(struct dispc_device *dispc, u16 idx, u32 val)
358 __raw_writel(val, dispc->base + idx);
375 enum mgr_reg_fields regfld, int val)
379 REG_FLD_MOD(dispc, rfld->reg, val, rfld->high, rfld->low);
961 u32 val;
966 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
968 dispc_write_reg(dispc, DISPC_OVL_POSITION(plane), val);
975 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
978 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val);
980 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val);
987 u32 val;
991 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
994 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val);
996 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val);
1149 u32 val;
1166 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1199 val = FLD_MOD(val, chan, shift, shift);
1200 val = FLD_MOD(val, chan2, 31, 30);
1202 val = FLD_MOD(val, channel, shift, shift);
1204 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val);
1211 u32 val;
1227 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1229 if (FLD_GET(val, shift, shift) == 1)
1235 switch (FLD_GET(val, 31, 30)) {
1334 u32 val;
1338 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1339 val = FLD_MOD(val, enable, 9, 9);
1340 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val);
1361 u32 val;
1363 val = FLD_VAL(height - 1, dispc->feat->mgr_height_start, 16) |
1366 dispc_write_reg(dispc, DISPC_SIZE_MGR(channel), val);
1642 u32 val;
1651 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1654 dispc_write_reg(dispc, DISPC_OVL_FIR(plane), val);
1656 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1657 dispc_write_reg(dispc, DISPC_OVL_FIR2(plane), val);
1665 u32 val;
1673 val = FLD_VAL(vaccu, vert_start, vert_end) |
1676 dispc_write_reg(dispc, DISPC_OVL_ACCU0(plane), val);
1683 u32 val;
1691 val = FLD_VAL(vaccu, vert_start, vert_end) |
1694 dispc_write_reg(dispc, DISPC_OVL_ACCU1(plane), val);
1701 u32 val;
1703 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1704 dispc_write_reg(dispc, DISPC_OVL_ACCU2_0(plane), val);
1711 u32 val;
1713 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1714 dispc_write_reg(dispc, DISPC_OVL_ACCU2_1(plane), val);
2147 u64 val, blank;
2173 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2175 val, max(0, ds - 2) * width);
2176 if (val < max(0, ds - 2) * width)
2184 val = div_u64((u64)nonactive * lclk, pclk);
2186 val, max(0, ds - 1) * width);
2187 if (val < max(0, ds - 1) * width)
3194 u32 mask, val;
3197 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3200 val <<= 16 + shifts[channel];
3203 mask, val);