Lines Matching defs:enable
628 /* enable last, because LCD & DIGIT enable are here */
638 * enable last so IRQs won't trigger before
700 enum omap_channel channel, bool enable)
702 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_ENABLE, enable);
737 bool enable, go;
739 enable = REG_GET(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
741 if (!enable)
1023 bool enable)
1028 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
1302 enum omap_channel channel, bool enable)
1307 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_CPR, enable);
1332 enum omap_plane_id plane, bool enable)
1339 val = FLD_MOD(val, enable, 9, 9);
1346 bool enable)
1355 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1501 void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable)
1504 WARN_ON(enable);
1508 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1509 REG_FLD_MOD(dispc, DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1560 enum omap_plane_id plane, bool enable)
1569 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
2907 enum omap_plane_id plane, bool enable)
2909 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2911 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2925 void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable)
2930 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2933 void dispc_pck_free_enable(struct dispc_device *dispc, bool enable)
2938 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2943 bool enable)
2945 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2979 enum omap_channel ch, bool enable)
2981 mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKENABLE, enable);
2986 bool enable)
2992 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 18, 18);
2994 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 19, 19);
3071 enum omap_channel channel, bool enable)
3073 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STALLMODE, enable);
3934 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
4684 /* Setup and enable GFX plane */
4689 /* Set up and enable display manager for LCD1 */