Lines Matching defs:channel
347 enum omap_channel channel);
349 enum omap_channel channel);
366 static u32 mgr_fld_read(struct dispc_device *dispc, enum omap_channel channel,
369 const struct dispc_reg_field *rfld = &mgr_desc[channel].reg_desc[regfld];
374 static void mgr_fld_write(struct dispc_device *dispc, enum omap_channel channel,
377 const struct dispc_reg_field *rfld = &mgr_desc[channel].reg_desc[regfld];
674 enum omap_channel channel)
676 return mgr_desc[channel].vsync_irq;
680 enum omap_channel channel)
682 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc->feat->no_framedone_tv)
685 return mgr_desc[channel].framedone_irq;
689 enum omap_channel channel)
691 return mgr_desc[channel].sync_lost_irq;
700 enum omap_channel channel, bool enable)
702 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_ENABLE, enable);
704 mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE);
708 enum omap_channel channel)
710 return !!mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE);
714 enum omap_channel channel)
716 return mgr_fld_read(dispc, channel, DISPC_MGR_FLD_GO) == 1;
719 void dispc_mgr_go(struct dispc_device *dispc, enum omap_channel channel)
721 WARN_ON(!dispc_mgr_is_enabled(dispc, channel));
722 WARN_ON(dispc_mgr_go_busy(dispc, channel));
724 DSSDBG("GO %s\n", mgr_desc[channel].name);
726 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_GO, 1);
1146 enum omap_channel channel)
1168 switch (channel) {
1202 val = FLD_MOD(val, channel, shift, shift);
1302 enum omap_channel channel, bool enable)
1304 if (channel == OMAP_DSS_CHANNEL_DIGIT)
1307 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_CPR, enable);
1311 enum omap_channel channel,
1316 if (!dss_mgr_is_lcd(channel))
1326 dispc_write_reg(dispc, DISPC_CPR_COEF_R(channel), coef_r);
1327 dispc_write_reg(dispc, DISPC_CPR_COEF_G(channel), coef_g);
1328 dispc_write_reg(dispc, DISPC_CPR_COEF_B(channel), coef_b);
1359 enum omap_channel channel, u16 width, u16 height)
1366 dispc_write_reg(dispc, DISPC_SIZE_MGR(channel), val);
2793 enum omap_channel channel)
2803 oi->fourcc, oi->rotation, channel, replication);
2805 dispc_ovl_set_channel_out(dispc, plane, channel);
2942 enum omap_channel channel,
2945 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2950 enum omap_channel channel)
2952 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STNTFT, 1);
2963 enum omap_channel channel, u32 color)
2965 dispc_write_reg(dispc, DISPC_DEFAULT_COLOR(channel), color);
2998 enum omap_channel channel,
3001 dispc_mgr_set_default_color(dispc, channel, info->default_color);
3002 dispc_mgr_set_trans_key(dispc, channel, info->trans_key_type,
3004 dispc_mgr_enable_trans_key(dispc, channel, info->trans_enabled);
3005 dispc_mgr_enable_alpha_fixed_zorder(dispc, channel,
3008 dispc_mgr_enable_cpr(dispc, channel, info->cpr_enable);
3009 dispc_mgr_set_cpr_coef(dispc, channel, &info->cpr_coefs);
3014 enum omap_channel channel,
3037 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_TFTDATALINES, code);
3071 enum omap_channel channel, bool enable)
3073 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STALLMODE, enable);
3077 enum omap_channel channel,
3082 dispc_mgr_enable_stallmode(dispc, channel, config->stallmode);
3083 dispc_mgr_enable_fifohandcheck(dispc, channel, config->fifohandcheck);
3085 dispc_mgr_set_clock_div(dispc, channel, &config->clock_info);
3087 dispc_mgr_set_tft_data_lines(dispc, channel, config->video_port_width);
3091 dispc_mgr_set_lcd_type_tft(dispc, channel);
3116 enum omap_channel channel,
3119 if (dss_mgr_is_lcd(channel))
3126 enum omap_channel channel,
3132 if (!_dispc_mgr_pclk_ok(dispc, channel, vm->pixelclock))
3135 if (dss_mgr_is_lcd(channel)) {
3151 enum omap_channel channel,
3164 dispc_write_reg(dispc, DISPC_TIMING_H(channel), timing_h);
3165 dispc_write_reg(dispc, DISPC_TIMING_V(channel), timing_v);
3185 dispc_write_reg(dispc, DISPC_POL_FREQ(channel), l);
3199 mask <<= 16 + shifts[channel];
3200 val <<= 16 + shifts[channel];
3219 enum omap_channel channel,
3226 DSSDBG("channel %d xres %u yres %u\n", channel, t.hactive, t.vactive);
3228 if (dispc_mgr_check_timings(dispc, channel, &t)) {
3233 if (dss_mgr_is_lcd(channel)) {
3234 _dispc_mgr_set_lcd_timings(dispc, channel, &t);
3264 dispc_mgr_set_size(dispc, channel, t.hactive, t.vactive);
3268 enum omap_channel channel, u16 lck_div,
3274 dispc_write_reg(dispc, DISPC_DIVISORo(channel),
3278 channel == OMAP_DSS_CHANNEL_LCD)
3283 enum omap_channel channel, int *lck_div,
3287 l = dispc_read_reg(dispc, DISPC_DIVISORo(channel));
3315 enum omap_channel channel)
3322 if (!dss_mgr_is_lcd(channel))
3325 src = dss_get_lcd_clk_source(dispc->dss, channel);
3339 lcd = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16);
3345 enum omap_channel channel)
3349 if (dss_mgr_is_lcd(channel)) {
3353 l = dispc_read_reg(dispc, DISPC_DIVISORo(channel));
3357 r = dispc_mgr_lclk_rate(dispc, channel);
3378 enum omap_channel channel;
3383 channel = dispc_ovl_get_channel_out(dispc, plane);
3385 return dispc_mgr_pclk_rate(dispc, channel);
3391 enum omap_channel channel;
3396 channel = dispc_ovl_get_channel_out(dispc, plane);
3398 return dispc_mgr_lclk_rate(dispc, channel);
3403 enum omap_channel channel)
3408 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3410 lcd_clk_src = dss_get_lcd_clk_source(dispc->dss, channel);
3412 seq_printf(s, "%s clk source = %s\n", mgr_desc[channel].name,
3415 dispc_mgr_get_lcd_divisor(dispc, channel, &lcd, &pcd);
3418 dispc_mgr_lclk_rate(dispc, channel), lcd);
3420 dispc_mgr_pclk_rate(dispc, channel), pcd);
3518 /* DISPC channel specific registers */
3735 enum omap_channel channel,
3741 dispc_mgr_set_lcd_divisor(dispc, channel, cinfo->lck_div,
3746 enum omap_channel channel,
3753 cinfo->lck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16);
3754 cinfo->pck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 7, 0);
3797 enum omap_channel channel)
3799 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3808 enum omap_channel channel)
3810 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3811 u32 *table = dispc->gamma_table[channel];
3814 DSSDBG("%s: channel %d\n", __func__, channel);
3852 enum omap_channel channel,
3856 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3857 u32 *table = dispc->gamma_table[channel];
3860 DSSDBG("%s: channel %d, lut len %u, hw len %u\n", __func__,
3861 channel, length, gdesc->len);
3896 dispc_mgr_write_gamma_table(dispc, channel);
3901 int channel;
3906 for (channel = 0; channel < ARRAY_SIZE(dispc->gamma_table); channel++) {
3907 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3910 if (channel == OMAP_DSS_CHANNEL_LCD2 &&
3914 if (channel == OMAP_DSS_CHANNEL_LCD3 &&
3923 dispc->gamma_table[channel] = gt;
3925 dispc_mgr_set_gamma(dispc, channel, NULL, 0);
4698 /* Enable and shut the channel to produce just one frame */