Lines Matching refs:args
149 struct nv_dma_v0 args = {};
208 args.target = NV_DMA_V0_TARGET_VM;
209 args.access = NV_DMA_V0_ACCESS_VM;
210 args.start = 0;
211 args.limit = chan->vmm->vmm.limit - 1;
219 args.target = NV_DMA_V0_TARGET_PCI;
220 args.access = NV_DMA_V0_ACCESS_RDWR;
221 args.start = nvxx_device(device)->func->
223 args.limit = args.start + device->info.ram_user - 1;
225 args.target = NV_DMA_V0_TARGET_VRAM;
226 args.access = NV_DMA_V0_ACCESS_RDWR;
227 args.start = 0;
228 args.limit = device->info.ram_user - 1;
232 args.target = NV_DMA_V0_TARGET_AGP;
233 args.access = NV_DMA_V0_ACCESS_RDWR;
234 args.start = chan->drm->agp.base;
235 args.limit = chan->drm->agp.base +
238 args.target = NV_DMA_V0_TARGET_VM;
239 args.access = NV_DMA_V0_ACCESS_RDWR;
240 args.start = 0;
241 args.limit = chan->vmm->vmm.limit - 1;
246 NV_DMA_FROM_MEMORY, &args, sizeof(args),
281 } args;
307 args.chan.version = 0;
308 args.chan.namelen = sizeof(args.name);
309 args.chan.runlist = __ffs64(runm);
310 args.chan.runq = 0;
311 args.chan.priv = priv;
312 args.chan.devm = BIT(0);
314 args.chan.vmm = 0;
315 args.chan.ctxdma = nvif_handle(&chan->push.ctxdma);
316 args.chan.offset = chan->push.addr;
317 args.chan.length = 0;
319 args.chan.vmm = nvif_handle(&chan->vmm->vmm.object);
321 args.chan.ctxdma = nvif_handle(&chan->push.ctxdma);
323 args.chan.ctxdma = 0;
324 args.chan.offset = ioffset + chan->push.addr;
325 args.chan.length = ilength;
327 args.chan.huserd = 0;
328 args.chan.ouserd = 0;
338 args.chan.huserd = nvif_handle(&chan->mem_userd.object);
339 args.chan.ouserd = 0;
347 snprintf(args.name, sizeof(args.name), "%s[%d]", name, task_pid_nr(current));
350 &args, sizeof(args), &chan->user);
356 chan->runlist = args.chan.runlist;
357 chan->chid = args.chan.chid;
358 chan->inst = args.chan.inst;
359 chan->token = args.chan.token;
368 struct nv_dma_v0 args = {};
379 } args;
381 args.host.version = 0;
382 args.host.type = NVIF_CHAN_EVENT_V0_KILLED;
386 &args.base, sizeof(args), &chan->kill);
399 args.target = NV_DMA_V0_TARGET_VM;
400 args.access = NV_DMA_V0_ACCESS_VM;
401 args.start = 0;
402 args.limit = chan->vmm->vmm.limit - 1;
404 args.target = NV_DMA_V0_TARGET_VRAM;
405 args.access = NV_DMA_V0_ACCESS_RDWR;
406 args.start = 0;
407 args.limit = device->info.ram_user - 1;
411 NV_DMA_IN_MEMORY, &args, sizeof(args),
417 args.target = NV_DMA_V0_TARGET_VM;
418 args.access = NV_DMA_V0_ACCESS_VM;
419 args.start = 0;
420 args.limit = chan->vmm->vmm.limit - 1;
423 args.target = NV_DMA_V0_TARGET_AGP;
424 args.access = NV_DMA_V0_ACCESS_RDWR;
425 args.start = chan->drm->agp.base;
426 args.limit = chan->drm->agp.base +
429 args.target = NV_DMA_V0_TARGET_VM;
430 args.access = NV_DMA_V0_ACCESS_RDWR;
431 args.start = 0;
432 args.limit = chan->vmm->vmm.limit - 1;
436 NV_DMA_IN_MEMORY, &args, sizeof(args),
537 } args = {
539 .m.count = sizeof(args.v) / sizeof(args.v.channels),
546 ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, &args, sizeof(args));
548 args.v.runlists.mthd == NV_DEVICE_INFO_INVALID || !args.v.runlists.data ||
549 args.v.channels.mthd == NV_DEVICE_INFO_INVALID)
552 drm->chan_nr = drm->chan_total = args.v.channels.data;
553 drm->runl_nr = fls64(args.v.runlists.data);
560 if (!(args.v.runlists.data & BIT(i)))
563 args.v.channels.mthd = NV_DEVICE_HOST_RUNLIST_CHANNELS;
564 args.v.channels.data = i;
566 ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, &args, sizeof(args));
567 if (ret || args.v.channels.mthd == NV_DEVICE_INFO_INVALID)
570 drm->runl[i].chan_nr = args.v.channels.data;