Lines Matching refs:regp
398 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
402 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC);
404 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, ®p->pllvals);
409 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11);
411 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL);
414 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630);
416 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634);
418 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP);
419 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL);
420 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW);
421 regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY);
422 regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL);
423 regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW);
424 regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY);
425 regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2);
429 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg);
430 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20);
434 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER);
436 regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4);
437 regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4);
441 regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
442 regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0);
446 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 &
449 regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1);
450 regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2);
452 regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR);
455 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0);
458 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20);
459 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24);
460 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34);
463 regp->ctv_regs[i] = NVReadRAMDAC(dev, head,
474 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
479 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
481 clk->pll_prog(clk, pllreg, ®p->pllvals);
486 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither);
488 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl);
491 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630);
493 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634);
495 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup);
496 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal);
497 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew);
498 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay);
499 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal);
500 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew);
501 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay);
502 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2);
507 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]);
508 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]);
512 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither);
514 NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]);
515 NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]);
519 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control);
520 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0);
521 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1);
522 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2);
524 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color);
527 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0);
530 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20);
531 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24);
532 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34);
536 NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]);
544 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
547 regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ);
550 rd_cio_state(dev, head, regp, i);
554 regp->Attribute[i] = NVReadVgaAttr(dev, head, i);
558 regp->Graphics[i] = NVReadVgaGr(dev, head, i);
561 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i);
568 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
571 NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg);
574 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]);
578 wr_cio_state(dev, head, regp, i);
582 NVWriteVgaGr(dev, head, i, regp->Graphics[i]);
586 NVWriteVgaAttr(dev, head, i, regp->Attribute[i]);
595 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
598 rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
599 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
600 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
601 rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
602 rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
603 rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
604 rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
606 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
607 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
608 rd_cio_state(dev, head, regp, NV_CIO_CRE_21);
611 rd_cio_state(dev, head, regp, NV_CIO_CRE_47);
614 rd_cio_state(dev, head, regp, 0x9f);
616 rd_cio_state(dev, head, regp, NV_CIO_CRE_49);
617 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
618 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
619 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
620 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
623 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830);
624 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834);
627 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT);
630 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850);
633 regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL);
634 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG);
637 regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG);
639 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
640 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
642 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
643 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
644 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B);
645 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
649 rd_cio_state(dev, head, regp, NV_CIO_CRE_42);
650 rd_cio_state(dev, head, regp, NV_CIO_CRE_53);
651 rd_cio_state(dev, head, regp, NV_CIO_CRE_54);
654 regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i);
655 rd_cio_state(dev, head, regp, NV_CIO_CRE_59);
656 rd_cio_state(dev, head, regp, NV_CIO_CRE_5B);
658 rd_cio_state(dev, head, regp, NV_CIO_CRE_85);
659 rd_cio_state(dev, head, regp, NV_CIO_CRE_86);
662 regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START);
671 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
681 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);
693 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
694 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);
695 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834);
698 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
701 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850);
704 if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC)
711 NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg);
713 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
714 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
715 wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
716 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
717 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
718 wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
719 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
720 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
721 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
724 wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
727 wr_cio_state(dev, head, regp, 0x9f);
729 wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
730 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
731 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
732 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
735 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
737 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
738 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
740 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
741 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
742 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B);
743 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
760 wr_cio_state(dev, head, regp, NV_CIO_CRE_42);
761 wr_cio_state(dev, head, regp, NV_CIO_CRE_53);
762 wr_cio_state(dev, head, regp, NV_CIO_CRE_54);
765 NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]);
766 wr_cio_state(dev, head, regp, NV_CIO_CRE_59);
767 wr_cio_state(dev, head, regp, NV_CIO_CRE_5B);
769 wr_cio_state(dev, head, regp, NV_CIO_CRE_85);
770 wr_cio_state(dev, head, regp, NV_CIO_CRE_86);
773 NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start);